公开(公告)号：US09455204B1

公开(公告)日：2016-09-27

申请号：US14727143

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy M. Cao ,  Jinping Liu ,  Guillaume Bouche ,  Huang Liu

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method of introducing N/P dopants in PMOS and NMOS fins at the SSRW layer without complicated processing and the resulting device are provided. Embodiments include forming a plurality of p-type and n-type fins on a substrate, the plurality of p-type and n-type fins formed with an ISSG or pad oxide layer; performing an n-well implant into the substrate through the ISSG or pad oxide layer; performing a first SRPD on the ISSG or pad oxide layer of the plurality of p-type fins; performing a p-well implant into the substrate through the ISSG or pad oxide layer; performing a second SRPD on the ISSG or pad oxide layer of the plurality of n-type fins; and driving the n-well and p-well implants and the SRPD dopants into a portion of the plurality of p-type and n-type fins.

Abstract translation: 在SSRW层的PMOS和NMOS鳍片中引入N / P掺杂剂而不需要复杂的处理并提供所得到的器件的方法。 实施例包括在基板上形成多个p型和n型翅片，多个p型和n型翅片形成有ISSG或衬垫氧化物层; 通过ISSG或衬垫氧化物层将n阱注入到衬底中; 在多个p型翅片的ISSG或衬垫氧化物层上执行第一SRPD; 通过ISSG或垫氧化物层进行p阱注入到衬底中; 在所述多个n型鳍片的ISSG或衬垫氧化物层上执行第二SRPD; 并且将n阱和p阱注入和SRPD掺杂剂驱动到多个p型和n型鳍中的一部分中。

公开(公告)号：US09431512B2

公开(公告)日：2016-08-30

申请号：US14308257

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L21/336 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/66439 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/775

Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

Abstract translation: 形成纳米线器件的方法包括在半导体衬底之上形成半导体材料层，在半导体材料层之上形成栅极结构，形成与栅极结构相邻的第一侧壁间隔物，并形成邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括使半导体材料层图案化，使得每个层具有第一和第二暴露的端表面。 栅极结构，第一侧壁间隔件和第二侧壁间隔件在图案化工艺期间被组合用作蚀刻掩模。 该方法还包括去除第一和第二侧壁间隔物，从而暴露图案化的半导体材料层的至少一部分。 该方法还包括在除去第一和第二侧壁间隔物之后，在至少图案化的半导体材料层的暴露部分中形成掺杂的延伸区域。

公开(公告)号：US09425097B1

公开(公告)日：2016-08-23

申请号：US14699154

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Wei ,  Sudharshanan Raghunathan

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

Abstract translation: 在Mx线之前光刻地切割Mx线的方法通过图案化光刻定义，并且提供所得到的2DSAV器件。 实施例包括在SiO 2层上形成a-Si虚拟金属层; 在所述a-Si虚拟金属层上形成第一软掩模堆叠; 将通过第一软掩模堆叠的多个通孔图形化成SiO 2层; 移除第一软掩模层; 在a-Si虚拟金属层上形成第一和第二蚀刻停止层，形成在多个通孔中的第一蚀刻停止层; 在第二蚀刻停止层上形成a-Si心轴; 在每个a-Si心轴的相对侧上形成氧化物间隔物; 去除a-Si心轴; 在氧化物间隔物下面的a-Si虚拟金属层中形成a-Si虚拟金属线; 并在a-Si虚拟金属线之间形成SiOC层。

公开(公告)号：US09412655B1

公开(公告)日：2016-08-09

申请号：US14608377

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Vikrant Chauhan ,  Andy C. Wei

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/3081 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

Abstract translation: 一种方法包括形成埋在第一介电层中的多条牺牲线。 在形成在第一电介质层上方的硬掩模层中形成线合并开口和线切口。 去除由线合并开口露出的第一电介质层的部分以限定线合并凹槽。 通过线切割开口暴露的所选牺牲线的一部分被去除以在所选牺牲线的第一和第二段之间限定线切割凹槽。 第二介质层形成在线切割凹部中。 硬面膜被去除。 多个牺牲线被导电材料代替，以限定在先前由第一和第二段占据的位置中限定具有第三和第四段的至少一个线，并且在线合并凹槽中限定线路合并导电结构。

公开(公告)号：US20160225666A1

公开(公告)日：2016-08-04

申请号：US14608377

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Vikrant Chauhan ,  Andy C. Wei

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3081 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

Abstract translation: 一种方法包括形成埋在第一介电层中的多条牺牲线。 在形成在第一电介质层上方的硬掩模层中形成线合并开口和线切口。 去除由线合并开口露出的第一电介质层的部分以限定线合并凹槽。 通过线切割开口暴露的所选牺牲线的一部分被去除以在所选牺牲线的第一和第二段之间限定线切割凹槽。 第二介质层形成在线切割凹部中。 硬面膜被去除。 多个牺牲线被导电材料代替，以限定在先前由第一和第二段占据的位置中限定具有第三和第四段的至少一个线，并且在线合并凹槽中限定线路合并导电结构。

公开(公告)号：US09305785B2

公开(公告)日：2016-04-05

申请号：US14318901

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Gabriel Padron Wells ,  Xiang Hu

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/06 ,  H01L23/535 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.

Abstract translation: 本发明的实施例提供了改进的接触形成的结构和方法。 在与翅片间隔开的区域中，从栅极去除顶盖氮化物。 这有助于减少处理步骤，允许栅极和源极/漏极区域以相同的工艺步骤打开。 可以使用极紫外光刻（EUVL）来形成抗蚀剂以形成接触。

公开(公告)号：US20200286998A1

公开(公告)日：2020-09-10

申请号：US16883492

申请日：2020-05-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/161 ,  H01L29/16 ,  H01L23/482 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

公开(公告)号：US10566248B1

公开(公告)日：2020-02-18

申请号：US16047044

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Chanro Park ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06

Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.

公开(公告)号：US20190139823A1

公开(公告)日：2019-05-09

申请号：US15804006

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Jason E. Stephens ,  Lars W. Liebmann ,  Guillaume Bouche

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/3213

Abstract: One illustrative method disclosed herein may include forming first and second via openings and forming conductive material for first and second conductive vias across substantially an entirety of an upper surface of a layer of insulating material and in the via openings. A patterned line etch mask layer is then formed above the conductive material, the etch mask having a first feature corresponding to a first conductive line and a second feature corresponding to a second conductive line, and performing at least one etching process to define the first and second conductive lines that are arranged in a tip-to-tip configuration. In this example, a first edge of the first conductive via is substantially aligned with a first end of the first conductive line and a second edge of the second conductive via is substantially aligned with a second end of the second conductive line.

公开(公告)号：US10229850B1

公开(公告)日：2019-03-12

申请号：US15860231

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche

IPC: H01L21/033 ,  H01L21/768

Abstract: Methods of patterning a structure. A first hardmask layer is deposited on a second hardmask layer. A cut is formed that penetrates through the first hardmask layer and the second hardmask layer. A block mask is formed in the cut. The first hardmask layer is patterned to form first lines penetrating through the first hardmask layer to the second hardmask layer with at least one of the first lines superimposed on the block mask. After patterning the first hardmask layer, the second hardmask layer is patterned to transfer the first lines from the first hardmask layer to the second hardmask layer to form second lines penetrating through the second hardmask layer. The second hardmask layer is etched with an isotropic etching process that removes the second hardmask layer selective to the first hardmask layer such that the second lines are widened relative to the first lines.