公开(公告)号：US09324618B1

公开(公告)日：2016-04-26

申请号：US14727364

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Bruce Doris

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a substrate fin, forming a layer of insulating material in the trenches, and forming a layer of CTE-matching material above the upper surface of the layer of insulating material, wherein the layer of CTE-matching material has a CTE that is within ±20% of the replacement fin CTE and wherein the layer of CTE-matching material partially defines a replacement fin cavity that exposes an upper portion of the substrate fin. In this example, the method also includes forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 一种说明性方法包括在半导体衬底中形成多个沟槽，以便限定衬底鳍，在沟槽中形成绝缘材料层，并在上表面上方形成一层CTE匹配材料 所述绝缘材料层，其中所述CTE匹配材料层具有在替换翅片CTE的±20％内的CTE，并且其中所述CTE匹配材料层部分地限定了将所述CTE匹配材料的上部 底片 在该示例中，该方法还包括在基板翅片和替换翅片腔上形成替换翅片，去除CTE匹配材料层并在替换翅片的至少一部分周围形成栅极结构。

公开(公告)号：US20150340468A1

公开(公告)日：2015-11-26

申请号：US14283721

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Min Gyu Sung ,  Jody A. Fronheiser ,  Christopher M. Prindle

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method includes forming at least one fin in a semiconductor substrate. A sacrificial gate structure is formed around a first portion of the at least one fin. Sidewall spacers are formed adjacent the sacrificial gate structure. The sacrificial gate structure and spacers expose a second portion of the at least one fin. An epitaxial material is formed on the exposed second portion. At least one process operation is performed to remove the sacrificial gate structure and thereby define a gate cavity between the spacers that exposes the first portion of the at least one fin. The first portion of the at least one fin is recessed to a first height less than a second height of the second portion of the at least one fin. A replacement gate structure is formed within the gate cavity above the recessed first portion of the at least one fin.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 在所述至少一个翅片的第一部分周围形成牺牲栅极结构。 侧壁间隔件形成在牺牲栅极结构附近。 所述牺牲栅极结构和间隔物暴露所述至少一个翅片的第二部分。 在暴露的第二部分上形成外延材料。 执行至少一个处理操作以去除牺牲栅极结构，从而在间隔件之间限定暴露至少一个鳍片的第一部分的栅极腔。 所述至少一个翅片的第一部分凹陷到小于所述至少一个翅片的第二部分的第二高度的第一高度。 在所述至少一个翅片的凹入的第一部分上方的栅极空腔内形成替换栅极结构。

公开(公告)号：US20170033181A1

公开(公告)日：2017-02-02

申请号：US14810574

申请日：2015-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy J. McArdle ,  Judson R. Holt ,  Bharat V. Krishnan ,  Jody A. Fronheiser

IPC: H01L29/10 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/1054 ,  H01L21/02107 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.

Abstract translation: 本文中公开的一种说明性方法包括在衬底翅片腔中单独形成不同半导体材料的交替层，以在凹陷衬底鳍上方形成多层鳍，其中形成不同半导体材料的各层 到最终厚度小于所形成的不同半导体材料的层的临界厚度，使绝缘材料层凹陷，以便将多层鳍片的至少一部分暴露在层的凹陷的上表面上方 绝缘材料并围绕暴露的多层鳍片的至少一部分形成栅极结构。

公开(公告)号：US09530869B2

公开(公告)日：2016-12-27

申请号：US14643409

申请日：2015-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Steven Bentley

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract translation: 本文公开的一种说明性方法包括在器件的源极/漏极区域中形成绝缘材料层，其中绝缘材料层具有与栅极盖层的上表面基本上平面的上表面 使绝缘材料层凹陷，使得其凹陷的上表面暴露在鳍片的表面上，执行另一蚀刻工艺以移除鳍片的至少一部分，从而限定位于凹鳍片上方的凹陷散热片沟槽，并形成外延 所述半导体材料至少部分地位于所述凹陷散热片沟槽中。

公开(公告)号：US20160351681A1

公开(公告)日：2016-12-01

申请号：US14727458

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Bruce Doris

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/7846 ,  H01L29/7848

Abstract: One method disclosed herein includes, among other things, forming a patterned fin having a thickness that is equal to or greater than a target final fin height for a replacement fin, performing an etching process through the patterned fin etch mask to form a plurality of trenches in a semiconductor substrate to define a substrate fin and forming a recessed layer of insulating material in the trenches so as to expose the patterned fin etch. The method also includes forming a layer of CTE-matching material around the exposed patterned fin etch mask, removing the patterned fin etch mask to thereby define a replacement fin cavity and expose a surface of the substrate fin, forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种方法包括形成具有等于或大于用于替换翅片的目标最终翅片高度的厚度的图案化翅片，通过图案化翅片蚀刻掩模执行蚀刻工艺以形成多个沟槽 在半导体衬底中限定衬底鳍并在沟槽中形成绝缘材料的凹陷层，以暴露图案化鳍片蚀刻。 该方法还包括在暴露的图案化鳍状物蚀刻掩模周围形成CTE匹配材料层，去除图案化的鳍状蚀刻掩模，从而限定替换的翅片腔并暴露衬底鳍片的表面，在衬底鳍片上形成置换鳍片 并且在替换翅片腔中，去除CTE匹配材料层并在替换翅片的至少一部分周围形成栅极结构。

公开(公告)号：US20160204261A1

公开(公告)日：2016-07-14

申请号：US15073936

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括围绕初始鳍片的一部分形成牺牲栅极结构，在牺牲栅极结构的相对侧上形成侧壁间隔物，并去除牺牲栅极 结构，从而限定替换栅极腔，通过替代栅极腔执行蚀刻工艺以去除初始翅片的部分，从而限定在侧壁间隔物下方的减小尺寸的翅片和凹陷，形成至少一个替代外延半导体 在更换的浇口腔体和侧壁间隙的凹槽内围绕减小尺寸的翅片的覆层材料，以及在至少一个替代的外延半导体包层材料周围的置换栅极腔内形成替换栅极结构。

公开(公告)号：US09343300B1

公开(公告)日：2016-05-17

申请号：US14686857

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Michael Hargrove ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/324 ,  H01L29/167 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/225

CPC classification number: H01L29/66636 ,  H01L21/02579 ,  H01L21/02694 ,  H01L21/2251 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.

Abstract translation: 本公开涉及在具有含锗沟道区的PMOS晶体管器件的沟道区域和源极/漏极区域之间形成相对突然的结。 在预先形成的源/漏腔之前，在衬层之上的源极/漏极腔中形成外延半导体材料之前形成衬层。 用于衬里层的材料，特别是锗的浓度（如果有的话）相对于沟道区域和外延源/漏极材料中的锗浓度进行调节，使得在退火过程期间，掺杂剂材料（例如 ，硼）在退火工艺期间从源极/漏极区扩散倾向于积聚在衬里层中或其附近。

公开(公告)号：US20160118251A1

公开(公告)日：2016-04-28

申请号：US14525351

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract translation: 本文中公开的一种说明性方法包括进行第一和第二原位掺杂，外延沉积工艺以分别在半导体衬底之上形成第一和第二层原位掺杂的外延半导体材料，其中第一和第二 层具有高水平的锗和低水平的P型掺杂剂材料，并且第一和第二层中的另一层具有低水平的锗和高水平的P型掺杂剂材料，并且进行混合热退火工艺 在第一和第二层上形成具有高水平的锗和高水平的P型掺杂剂材料的最终硅锗材料。

公开(公告)号：US20150318169A1

公开(公告)日：2015-11-05

申请号：US14267634

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  David Paul Brunco

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate and performing an epitaxial deposition process using a combination of silane (SiH4), dichlorosilane (SiH2Cl2), germane (GeH4) and a carrier gas to form an epi semiconductor material around the fin, wherein the flow rate of dichlorosilane used during the epitaxial deposition process is equal to 10-90% of the combined flow rate of silane and dichlorosilane.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片并使用硅烷（SiH 4），二氯硅烷（SiH 2 Cl 2），锗烷（GeH 4）和载气的组合进行外延沉积工艺以形成外延 散热片周围的半导体材料，其中在外延沉积工艺期间使用的二氯硅烷的流速等于硅烷和二氯硅烷的组合流速的10-90％。

公开(公告)号：US09165767B2

公开(公告)日：2015-10-20

申请号：US14071170

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jody A. Fronheiser ,  Jinping Liu ,  Bongki Lee

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延生长在增加的（100）区域。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长附加外延的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并，同时 也增加了他们的体积。