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    CMP head structure
    21.
    发明授权
    CMP head structure 有权
    CMP头结构

    公开(公告)号：US09242341B2

    公开(公告)日：2016-01-26

    申请号：US14059451

    申请日：2013-10-22

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu Lin ,  Wei Lu ,  Alex See

    IPC: B24B49/00 ,  B24B37/005 ,  B24B37/32

    CPC classification number: B24B49/00 ,  B24B37/005 ,  B24B37/32

    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

    Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在台板上的抛光垫; 用于将晶片保持在抛光垫上的头组件，其中所述头组件包括所述保持环; 用于感测保持环和其膜之间的台阶高度的传感器和用于根据保持环与其膜之间的台阶高度来调节保持环的运动的控制器，以确保台阶高度保持在固定值，作为保持 戒指磨损了。

    INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS FOR FABRICATING SAME
    22.
    发明申请
    INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS FOR FABRICATING SAME 有权
    具有改进的GAP膜电介质的集成电路及其制造方法

    公开(公告)号：US20150187641A1

    公开(公告)日：2015-07-02

    申请号：US14145581

    申请日：2013-12-31

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lei Wang ,  Lup San Leong ,  Wei Lu ,  Alex See

    IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

    CPC classification number: H01L21/76819 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/76805 ,  H01L21/76837 ,  H01L21/76879 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.

    Abstract translation: 提供具有减少短路的集成电路和制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括沉积覆盖半导体衬底的间隙填充电介质。 间隙填充电介质形成有具有高度差的上表面。 该方法包括减小间隙填充电介质的上表面的高度差。 此外，该方法包括沉积覆盖间隙填充电介质的层间电介质。 此外，该方法形成与覆盖半导体衬底的选定位置的电接触。

    CD control
    23.
    发明授权
    CD control 有权
    CD控制

    公开(公告)号：US08836139B2

    公开(公告)日：2014-09-16

    申请号：US13655408

    申请日：2012-10-18

    Applicant: Globalfoundries Singapore Pte. Ltd.

    Inventor： Zheng Zou ,  Alex See ,  Huang Liu ,  Hai Cong

    IPC: H01L21/302 ,  H01L21/768 ,  H01L23/48

    CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.

    Abstract translation: 一种方法包括在第一层上提供具有图案化的第二层的衬底。 第二层包括具有等于由光刻系统（CDL）产生的CD的第一CD的第二层开口。 CDL大于所需的CD（CDD）。 形成第三层以填充开口，留下第二层的顶表面露出。 去除第二层以产生由第三层形成的台面。 台面的CD等于第一张CD。 台面被修剪以产生具有等于约CDD的第二CD的台面。 形成第四层以覆盖第一层，留下台面的顶部。 蚀刻衬底以去除台面和台面下面的第一层的一部分以在具有CDD的第一层中形成开口。

    Integrated two-terminal device with logic device for embedded application
    24.
    发明授权
    Integrated two-terminal device with logic device for embedded application 有权

    公开(公告)号：US10446607B2

    公开(公告)日：2019-10-15

    申请号：US15393200

    申请日：2016-12-28

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Wanbing Yi ,  Curtis Chun-I Hsieh ,  Juan Boon Tan ,  Soh Yun Siah ,  Hai Cong ,  Alex See ,  Young Seon You ,  Danny Pak-Chum Shum ,  Hyunwoo Yang

    IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12

    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.

    Small pitch and high density contact array
    25.
    发明授权
    Small pitch and high density contact array 有权
    小间距和高密度接触阵列

    公开(公告)号：US09543502B2

    公开(公告)日：2017-01-10

    申请号：US14720856

    申请日：2015-05-25

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Zheng Zou ,  Alex See

    IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

    CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

    Abstract: A method of forming high density contact array is disclosed. The method includes providing a first dielectric layer and forming a hard mask stack over the first dielectric layer. The hard mask stack includes first, second and third hard mask layers. The first and second hard mask layers are processed to form high density array of hard mask stack structures using a double patterning process. The hard mask stack structures include patterned first and second hard mask layers having a first width F1. The width of the patterned second hard mask layers is reduced to a second width F2 to form high density array of hard mask posts. A fourth hard mask layer is formed over the third hard mask layer and surrounding the hard mask posts. The hard mask posts and portions of the third hard mask layer and first dielectric layer underlying the hard mask posts are removed to form high density contact hole array.

    Abstract translation: 公开了形成高密度接触阵列的方法。 该方法包括提供第一电介质层并在第一电介质层上形成硬掩模叠层。 硬掩模叠层包括第一，第二和第三硬掩模层。 处理第一和第二硬掩模层以形成使用双重图案化工艺的硬掩模叠层结构的高密度阵列。 硬掩模叠层结构包括具有第一宽度F1的图案化的第一和第二硬掩模层。 图案化的第二硬掩模层的宽度被减小到第二宽度F2以形成高密度阵列的硬掩模柱。 第四硬掩模层形成在第三硬掩模层上并围绕硬掩模柱。 去除硬掩模柱和硬掩模柱下面的第三硬掩模层和第一介电层的部分以形成高密度接触孔阵列。

    CMP HEAD STRUCTURE
    28.
    发明申请
    CMP HEAD STRUCTURE 有权

    公开(公告)号：US20160136781A1

    公开(公告)日：2016-05-19

    申请号：US15005029

    申请日：2016-01-25

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu Lin ,  Wei Lu ,  Alex See

    IPC: B24B49/00

    CPC classification number: B24B49/00 ,  B24B37/005 ,  B24B37/32

    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

    Through silicon vias
    29.
    发明授权
    Through silicon vias 有权
    通过硅通孔

    公开(公告)号：US09287197B2

    公开(公告)日：2016-03-15

    申请号：US13831898

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu Lin ,  Hong Yu ,  Lup San Leong ,  Alex See ,  Wei Lu

    IPC: H01L21/44 ,  H01L21/00 ,  H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/535 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

    Abstract translation: 公开了一种用于形成装置的装置和方法。 提供衬底，并且通过衬底的顶表面在衬底中形成TSV。 衬底的TSV和顶表面衬有具有第一绝缘层，抛光停止层和第二绝缘层的绝缘堆叠。 在基板上形成导电层。 TSV填充有导电层的导电材料。 将衬底平坦化以除去导电层的过量导电材料。 平坦化停止在抛光停止层上以形成平坦的顶表面。

    Integrated circuits with memory cells and methods of manufacturing the same
    30.
    发明授权
    Integrated circuits with memory cells and methods of manufacturing the same 有权
    具有存储单元的集成电路及其制造方法

    公开(公告)号：US09209275B1

    公开(公告)日：2015-12-08

    申请号：US14445279

    申请日：2014-07-29

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Zheng Zou ,  Alex See

    IPC: H01L29/788 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L27/115 ,  H01L21/28 ,  H01L21/285

    CPC classification number: H01L21/28518 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7881

    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes removing a central plug from between a first memory cell and a second memory cell to define a center gap. Each of the first and second memory cells include a control gate with a control gate height, a cap overlying the control gate, a select gate adjacent to the control gate, and a select gate dielectric between the control gate and the select gate. The select gate is recessed to a select gate height while the cap overlies the control gate, where the select gate height is less than the control gate height. A memory spacer is formed overlying the select gate dielectric and adjacent to the control gate.

    Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括从第一存储单元和第二存储单元之间移除中心插塞以限定中心间隙。 第一和第二存储单元中的每一个包括具有控制栅极高度的控制栅极，覆盖控制栅极的盖子，与控制栅极相邻的选择栅极以及控制栅极与选择栅极之间的选择栅极电介质。 选择栅极凹入选择栅极高度，而盖子覆盖控制栅极，其中选择栅极高度小于控制栅极高度。 存储器间隔件形成在选择栅极电介质上并且邻近控制栅极。

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