公开(公告)号：US20050159018A1

公开(公告)日：2005-07-21

申请号：US11078537

申请日：2005-03-10

申请人： Garo Derderian ,  Gurtej Sandhu

发明人： Garo Derderian ,  Gurtej Sandhu

IPC分类号： C23C16/44 ,  C23C16/455 ,  H01L21/285 ,  H01L21/31 ,  H01L21/44 ,  H01L21/469

CPC分类号： C23C16/45536 ,  C23C16/44 ,  H01L21/28562

摘要： The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.

摘要翻译： 本发明包括这样的方法，其中至少两种不同的前体相对于彼此以不同的和基本上不重叠的时间流入反应室，以在基底的至少一部分上形成材料，并且其中至少一个 前体在物理性质方面是不对称的。 影响不对称物理性质的场定向在反应室内，并且用于影响形成材料时具有不对称性质的前体的取向。 不对称物理性质可以是例如与前体相关的各向异性电荷分布，在这种方面，用于影响不对称物理性质的场可以是在反应室内提供的电场和/或提供的磁场 在反应室内。 本发明的方法可用于原子层沉积工艺。

公开(公告)号：US20050042374A1

公开(公告)日：2005-02-24

申请号：US10652224

申请日：2003-08-22

申请人： Demetrius Sarigiannis ,  Garo Derderian ,  Cem Basceri

发明人： Demetrius Sarigiannis ,  Garo Derderian ,  Cem Basceri

IPC分类号： C23C16/40 ,  C23C16/44 ,  C23C16/448 ,  C23C16/455 ,  C23C16/06

CPC分类号： C23C16/45525 ,  C23C16/40 ,  C23C16/448 ,  Y10S427/101

摘要： The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is utilized to introduce at least one precursor into a chamber during ALD, and in particular aspects the supercritical fluid is utilized to introduce multiple precursors into the reaction chamber during ALD. The invention can be utilized to form any of various materials, including metal-containing materials, such as, for example, metal oxides, metal nitrides, and materials consisting of metal. Metal oxides can be formed by utilizing a supercritical fluid can be utilized to introduce a metal-containing precursor into reaction chamber, with the precursor then forming a metal-containing layer over a surface of a substrate. Subsequently, the metal-containing layer can be reacted with oxygen to convert at least some of the metal within the layer to metal oxide.

摘要翻译： 本发明包括利用超临界流体将前体引入反应室的方法。 在一些方面，使用超临界流体在ALD期间将至少一种前体引入室中，并且在特定方面，超临界流体用于在ALD期间将多种前体引入反应室。 本发明可用于形成任何各种材料，包括含金属的材料，例如金属氧化物，金属氮化物和由金属组成的材料。 可以通过利用超临界流体来形成金属氧化物，以将含金属的前体引入反应室，然后前体在基材的表面上形成含金属的层。 随后，含金属层可以与氧反应以将该层内的至少一些金属转化为金属氧化物。

公开(公告)号：US06596583B2

公开(公告)日：2003-07-22

申请号：US10002906

申请日：2001-10-29

申请人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

发明人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  H01L21/31637 ,  H01L28/55 ,  H01L28/65

摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

公开(公告)号：US08587989B2

公开(公告)日：2013-11-19

申请号：US12486602

申请日：2009-06-17

申请人： H. Montgomery Manning ,  Thomas Rueckes ,  Claude L. Bertin ,  Jonathan W. Ward ,  Garo Derderian

发明人： H. Montgomery Manning ,  Thomas Rueckes ,  Claude L. Bertin ,  Jonathan W. Ward ,  Garo Derderian

IPC分类号： G11C13/00

CPC分类号： G11C13/025 ,  B82Y10/00 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1675

摘要： NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in electrical communication with first and second conductor layers. A memory operation circuit including a circuit for generating and applying a select signal on first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers is provided. At least two adjacent memory cells are formed in at least two selected cross sections of the nanotube fabric and conductor layers such that each memory cell is uniquely addressable and programmable. For each cell, a change in resistance corresponds to a change in an informational state of the memory cell. Some embodiments include bit lines, word lines, and reference lines. In some embodiments, 6F2 memory cell density is achieved.

摘要翻译： 公开了具有纳米管块，轨迹和平面的NRAM阵列及其制造方法。 在一些实施例中，纳米管存储器阵列包括布置成与第一和第二导体层电连通的纳米管织物层。 一种存储器操作电路，包括用于在第一和第二导体层上产生和施加选择信号以引起第一和第二导体层之间的纳米管织物层的电阻变化的电路。 至少两个相邻的存储单元形成在纳米管织物和导体层的至少两个选定的横截面中，使得每个存储单元是唯一可寻址和可编程的。 对于每个单元，电阻变化对应于存储单元的信息状态的变化。 一些实施例包括位线，字线和参考线。 在一些实施例中，实现6F2存储单元密度。

公开(公告)号：US20090067256A1

公开(公告)日：2009-03-12

申请号：US11899644

申请日：2007-09-06

申请人： Arup Bhattacharyya ,  Garo Derderian

发明人： Arup Bhattacharyya ,  Garo Derderian

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L29/42324 ,  G11C2207/2245 ,  H01L29/40114 ,  H01L29/40117

摘要： Embodiments are described for reducing the programming voltage of a memory cell in a memory device. The memory cell includes a channel region extending between first and second diffusion regions formed in a substrate. A tunnel dielectric material is formed over the channel region. A storage medium is formed over the tunnel dielectric material to store electrical charge. The storage medium is disposed between a first interface material and a second interface material, each interface material provides a smoother interface between the storage medium and surrounding dielectric materials. A charge blocking material is formed over the storage medium, followed by a control gate material.

摘要翻译： 描述了用于降低存储器件中的存储器单元的编程电压的实施例。 存储单元包括在衬底中形成的第一和第二扩散区之间延伸的沟道区。 在沟道区上形成隧道介电材料。 在隧道电介质材料上形成存储介质以存储电荷。 存储介质设置在第一界面材料和第二界面材料之间，每个界面材料在存储介质和周围介质材料之间提供更平滑的界面。 在存储介质上形成电荷阻挡材料，随后形成控制栅极材料。

公开(公告)号：US20060257570A1

公开(公告)日：2006-11-16

申请号：US11490622

申请日：2006-07-21

申请人： Garo Derderian ,  Gurtej Sandhu

发明人： Garo Derderian ,  Gurtej Sandhu

IPC分类号： C23C16/00

CPC分类号： C23C16/45525 ,  B05D1/185 ,  C23C16/04 ,  C23C16/045 ,  C23C16/403 ,  C23C16/45531 ,  C30B25/18 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3162

摘要： A deposition method includes contacting a substrate with a first initiation precursor and forming a first portion of an initiation layer on the substrate. At least a part of the substrate is contacted with a second initiation precursor different from the first initiation precursor and a second portion of the initiation layer is formed on the substrate. The substrate may be simultaneously contacted with a plurality of initiation precursors, forming on the substrate and initiation layer comprising components, derived from each of the plurality of initiation precursors. An initiation layer may be contacted with a deposition precursor, forming a deposition layer on the initiation layer. The deposition layer may be contacted with a second initiation precursor different from the first initiation precursor forming a second initiation layer over the substrate. Also, a first initiation layer may be formed substantially selectively on a first-type substrate surface relative to a second-type substrate surface and contacted with a deposition precursor, forming a deposition layer substantially selectively over the first-type substrate surface.

摘要翻译： 沉积方法包括使基底与第一起始前体接触，并在基底上形成起始层的第一部分。 基板的至少一部分与不同于第一起始前体的第二起始前体接触，并且在基板上形成起始层的第二部分。 衬底可以与多个起始前体同时接触，在衬底上形成并且起始层包含衍生自多个引发前体中的每一个的组分。 引发层可以与沉积前体接触，在引发层上形成沉积层。 沉积层可以与不同于第一起始前体的第二引发前体接触，从而在衬底上形成第二起始层。 此外，第一起始层可以基本上选择性地形成在相对于第二类型衬底表面的第一类型衬底表面上，并与沉积前体接触，在第一类型衬底表面上基本上选择性地形成沉积层。

公开(公告)号：US20060240646A1

公开(公告)日：2006-10-26

申请号：US11472009

申请日：2006-06-21

申请人： Demetrius Sarigiannis ,  Cem Basceri ,  Christopher Hill ,  Garo Derderian

发明人： Demetrius Sarigiannis ,  Cem Basceri ,  Christopher Hill ,  Garo Derderian

IPC分类号： H01L21/48

CPC分类号： C23C16/4401 ,  C23C14/564

摘要： A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.

公开(公告)号：US20060043456A1

公开(公告)日：2006-03-02

申请号：US10932795

申请日：2004-09-02

申请人： Garo Derderian ,  Nirmal Ramaswamy

发明人： Garo Derderian ,  Nirmal Ramaswamy

IPC分类号： H01L29/76 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336

摘要： Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.

摘要翻译： 使用外延硅层来保护浮栅存储器单元的隧道介电层免于在形成浅沟槽隔离（STI）区域期间的过度氧化或去除。 在沟槽形成之后，外延硅层从隧道介电层的相对侧上的含硅层生长，从而允许其厚度被限制为隧道介电层的厚度的大约二分之一。 外延硅可以在用电介质材料填充沟槽之前被氧化，或者在氧化至少覆盖隧道介电层的端部的外延硅之前可能发生电介质填充。

公开(公告)号：US20060040480A1

公开(公告)日：2006-02-23

申请号：US10923315

申请日：2004-08-20

申请人： Garo Derderian ,  Donald Westmoreland ,  Stefan Uhlenbrook

发明人： Garo Derderian ,  Donald Westmoreland ,  Stefan Uhlenbrook

IPC分类号： H01L21/20

CPC分类号： H01L21/02205 ,  C23C16/405 ,  C23C16/45553 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/31604 ,  H01L28/90

摘要： A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.

摘要翻译： 使用一种或多种包括铌和/或钒的前体化合物在基板上，特别是用于制造半导体或存储器件结构的半导体衬底或衬底组件中形成（以及用于形成）含金属层的方法 以及使用包括多个沉积循环的原子层沉积工艺。

公开(公告)号：US20060019461A1

公开(公告)日：2006-01-26

申请号：US10895481

申请日：2004-07-20

申请人： Garo Derderian ,  Kevin Shea

发明人： Garo Derderian ,  Kevin Shea

IPC分类号： H01L21/20 ,  H01L21/302 ,  H01L21/31

CPC分类号： H01L21/02178 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/31616 ,  H01L28/40 ,  H01L28/56

摘要： This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen comprising material on the first capacitor electrode material. The dielectric silicon and nitrogen comprising material is exposed to an aqueous fluid comprising a base and an oxidizer. The aqueous fluid has a pH greater than 7.0. After the exposing to the aqueous fluid, an aluminum oxide comprising capacitor dielectric material is deposited over the first capacitor electrode material. A second capacitor electrode material is formed over the aluminum oxide comprising capacitor dielectric material. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括形成电容器的方法。 在一个实施方案中，在衬底上形成第一电容器电极材料。 将第一电容器电极材料暴露于含氮气氛中，有效地在第一电容器电极材料上形成电介质硅和氮的材料。 介电硅和氮的材料暴露于包含碱和氧化剂的含水流体。 含水流体的pH值大于7.0。 在暴露于含水流体之后，将包含电容器介电材料的氧化铝沉积在第一电容器电极材料上。 在包含电容器电介质材料的氧化铝上形成第二电容器电极材料。 考虑了其他方面和实现。