公开(公告)号：US06632747B2

公开(公告)日：2003-10-14

申请号：US09885600

申请日：2001-06-20

申请人： Hiroaki Niimi ,  Douglas T. Grider ,  Rajesh Khamankar ,  Sunil Hattangady

发明人： Hiroaki Niimi ,  Douglas T. Grider ,  Rajesh Khamankar ,  Sunil Hattangady

IPC分类号： H01L2131

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% 02); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.

摘要翻译： 本发明的一个实施例是通过提供具有半导体表面的衬底来形成超薄电介质层的方法; 在半导体表面上形成含氧层; 将含氧层暴露于含氮等离子体以在整个含氧层中产生均匀的氮分布; 并重新氧化和退火该层以稳定氮分布，治愈等离子体诱导的损伤并降低界面缺陷密度。该退火步骤选自一组四种再氧化技术：连续 在H 2和N 2（优选小于20％H 2）的混合物中进行退火，然后将O 2和N 2（优选小于20％的O 2）的混合物进行退火;通过尖峰状温度升高（优选小于20％ （优选为N 2 / O 2或N 2 O / H 2）;通过在减压下的氨中快速热加热（优选在600至1000℃下，对于 5至60秒）;在800至1050℃下在氧化剂/氢气混合物（优选N 2 O与1％H 2）中退火5至60秒。

公开(公告)号：US09177806B2

公开(公告)日：2015-11-03

申请号：US13017828

申请日：2011-01-31

申请人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

发明人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC分类号： H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49

CPC分类号： H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

摘要翻译： 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US20140070327A1

公开(公告)日：2014-03-13

申请号：US13609621

申请日：2012-09-11

申请人： Hiroaki Niimi ,  Seung-Chul Song

发明人： Hiroaki Niimi ,  Seung-Chul Song

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0928

摘要： A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.

摘要翻译： 互补金属氧化物半导体（CMOS）集成电路结构及其替代金属栅极工艺的制造方法。 P沟道和n沟道MOS晶体管由组成或厚度彼此不同的高k栅介质材料形成，并且在组成或厚度上彼此不同的界面电介质材料形成。 所描述的替代栅极处理使得能够构造，使得p沟道或n沟道晶体管栅极结构都不包括来自另一个晶体管的金属栅极材料，从而有助于用填充金属可靠地填充栅极结构。

公开(公告)号：US08617954B2

公开(公告)日：2013-12-31

申请号：US11856310

申请日：2007-10-09

申请人： Hiroaki Niimi ,  Manoj Mehrotra

发明人： Hiroaki Niimi ,  Manoj Mehrotra

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L21/3144 ,  H01L21/3185 ,  H01L21/3211 ,  H01L29/518 ,  H01L29/78

摘要： Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.

摘要翻译： 提供了一种制造栅极电介质的方法。 该方法，但不限于，包括使硅衬底经受第一等离子体氮化处理以在其中引入氮区域。 该方法还包括使用含氮氧化剂气体在氮区域上生长电介质材料层，并对电介质材料层进行第二等离子体氮化处理，从而在氮区域上形成氮化介电材料层。

公开(公告)号：US08482080B2

公开(公告)日：2013-07-09

申请号：US13475147

申请日：2012-05-18

申请人： Hiroaki Niimi ,  Huang-Chun Wen

发明人： Hiroaki Niimi ,  Huang-Chun Wen

IPC分类号： H01L31/119

CPC分类号： H01L21/823842 ,  H01L21/28202 ,  H01L21/823864 ,  H01L29/518 ,  H01L29/66545

摘要： A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.

摘要翻译： 公开了一种PMOS晶体管，其包括在PMOS晶体管中的栅极介电层和金属栅极之间的氧扩散的含氮势垒，与与含氮屏障直接接触的金属栅极的低氧区域和氧 金属栅极的富含区域在低含氧金属区域之上。 可以通过在栅极介电层上沉积含氮阻挡材料或通过氮化栅极电介质层的顶部区域来形成含氮屏障。 可以通过在金属栅极的低氧区域上沉积氧化金属或氧化金属栅极的低氧区域的顶部区域来形成金属栅极的富氧区域。

公开(公告)号：US08216913B2

公开(公告)日：2012-07-10

申请号：US12343780

申请日：2008-12-24

申请人： Hiroaki Niimi ,  Elisabeth Marley

发明人： Hiroaki Niimi ,  Elisabeth Marley

IPC分类号： H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

摘要： Adding nitrogen to the Si—SiO2 interface at STI sidewalls increases carrier mobility in MOS transistors, but control of the amount of nitrogen has been problematic due to loss of the nitrogen during liner oxide growth. This invention discloses a method of forming STI regions which have a controllable layer of nitrogen atoms at the STI sidewall interface. Nitridation is performed on the STI sidewalls by exposure to a nitrogen-containing plasma, by exposure to NH3 gas at high temperatures, or by deposition of a nitrogen-containing thin film. Nitrogen is maintained at a level of 1.0·1015 to 3.0·1015 atoms/cm2, preferably 2.0·1015 to 2.4·1015 atoms/cm2, at the interface after growth of a liner oxide by adding nitrogen-containing gases to an oxidation ambient. The density of nitrogen is adjusted to maximize stress in a transistor adjacent to the STI regions. An IC fabricated according to the inventive method is also disclosed.

摘要翻译： 在STI侧壁上向Si-SiO 2界面添加氮增加了MOS晶体管中的载流子迁移率，但是由于在衬里氧化物生长期间氮的损失，氮的量的控制是有问题的。 本发明公开了一种形成在STI侧壁界面具有可控氮原子层的STI区的方法。 通过暴露于含氮等离子体，通过在高温下暴露于NH 3气体，或通过沉积含氮薄膜，在STI侧壁上进行氮化。 在通过向氧化环境中加入含氮气体的衬垫氧化物生长之后的界面处，氮保持在1.0×10 15至3.0×10 15原子/ cm 2，优选2.0×10 15至2.4×10 15原子/ cm 2的水平。 调节氮的密度以使与STI区相邻的晶体管中的应力最大化。 还公开了根据本发明方法制造的IC。

公开(公告)号：US20120018810A1

公开(公告)日：2012-01-26

申请号：US13006185

申请日：2011-01-13

申请人： James Joseph Chambers ,  Hiroaki Niimi

发明人： James Joseph Chambers ,  Hiroaki Niimi

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/283 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.

摘要翻译： 一种具有NMOS晶体管的CMOS器件，其具有包括具有低功函数/高氧亲和性帽的中间间隙金属的金属栅极和具有金属栅电极的PMOS晶体管，该金属栅电极包括具有高功函数/低氧的中间间隙金属 亲和帽和成型方法。

公开(公告)号：US20090166747A1

公开(公告)日：2009-07-02

申请号：US12206324

申请日：2008-09-08

申请人： Hiroaki Niimi ,  Manuel Angel Quevedo-Lopez

发明人： Hiroaki Niimi ,  Manuel Angel Quevedo-Lopez

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors.

摘要翻译： 提供了半导体器件和制造方法，其中为MOS晶体管提供金属晶体管栅极。 在栅极电介质上方形成并入金属氮化物层的稀土 - 稀土合金。 该过程提供了栅电极功函数的调整，从而调谐所得NMOS晶体管的阈值电压。

公开(公告)号：US20080050882A1

公开(公告)日：2008-02-28

申请号：US11931529

申请日：2007-10-31

申请人： Malcolm Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam Alshareef

发明人： Malcolm Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam Alshareef

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

摘要翻译： 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US20070218636A1

公开(公告)日：2007-09-20

申请号：US11384753

申请日：2006-03-20

申请人： Hiroaki Niimi ,  Reima Laaksonen

发明人： Hiroaki Niimi ,  Reima Laaksonen

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active region of a semiconductor device, patterning the masking layer to expose the semiconductor substrate in the first active region, and subjecting exposed portions of the semiconductor substrate to a nitrogen containing plasma, thereby forming a first layer of gate dielectric material over the semiconductor substrate in the first active region. The method, in that embodiment, may further include incorporating oxygen into the first layer of gate dielectric material located in the first active region, and then removing the patterned masking layer, and forming a second layer of gate dielectric material over the first layer of gate dielectric material in the first active region and over the semiconductor substrate in the second active region, thereby resulting in a first greater thickness gate dielectric in the first active region and a second lesser thickness gate dielectric in the second active region.

摘要翻译： 本发明提供一种制造具有多个栅介质厚度层的半导体器件的方法。 在一个实施例中，该方法包括在半导体器件的第一有源区和第二有源区中的半导体衬底上形成掩模层，图案化掩模层以暴露第一有源区中的半导体衬底，并对暴露部分 从而在第一有源区中在半导体衬底上形成第一层栅极电介质材料层。 在该实施例中，该方法还可以包括将氧结合到位于第一有源区中的第一栅极电介质材料层中，然后去除图案化的掩模层，以及在第一层栅极上形成第二层栅极电介质材料层 第一有源区中的介电材料和第二有源区中的半导体衬底上方，从而在第一有源区中形成第一较大厚度的栅极电介质，以及在第二有源区中形成第二较小厚度的栅极电介质。