公开(公告)号：US20100171188A1

公开(公告)日：2010-07-08

申请号：US12349903

申请日：2009-01-07

申请人： Hsiang-Lan Lung ,  Erh-Kun Lai

发明人： Hsiang-Lan Lung ,  Erh-Kun Lai

IPC分类号： H01L29/78 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L27/1021 ,  H01L21/743 ,  H01L27/105 ,  H01L29/7827 ,  H01L29/861

摘要： A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process.

摘要翻译： 硅化物元件将单晶硅节点与底层硅衬底分开，并且能够用作用于互连器件上的器件的导电元件。 单晶硅节点可以作为二极管的一个端子，其顶部的第二个半导体节点可以作为二极管的另一个端子。 单晶硅节点可以用作晶体管的端子之一，并且第二和第三半导体节点在其顶部上串联形成，提供垂直晶体管结构，其可被配置为场效应晶体管或双极结型晶体管 。 硅化物元件可以通过利用硅化物形成工艺消耗突出的单晶元件的基底，同时屏蔽突出元件的上部从硅化物形成工艺形成的工艺。

公开(公告)号：US20100117048A1

公开(公告)日：2010-05-13

申请号：US12267453

申请日：2008-11-07

申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC分类号： H01L45/00 ,  H01L29/04 ,  H01L21/329

CPC分类号： H01L29/8616 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/04 ,  H01L29/165 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.

摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域，第一和 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区形成在单晶半导体中，并且所述第二掺杂半导体区包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与所述第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定所述第一和第二区域之间的pn结。

公开(公告)号：US08907316B2

公开(公告)日：2014-12-09

申请号：US12267453

申请日：2008-11-07

申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/102 ,  H01L27/24 ,  H01L29/861 ,  H01L29/165 ,  H01L29/04 ,  G11C13/00

CPC分类号： H01L29/8616 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/04 ,  H01L29/165 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.

摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域，第一和 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区形成在单晶半导体中，并且所述第二掺杂半导体区包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与所述第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定所述第一和第二区域之间的pn结。

公开(公告)号：US08664689B2

公开(公告)日：2014-03-04

申请号：US12267492

申请日：2008-11-07

申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC分类号： H01L29/861 ,  H01L29/88

CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

公开(公告)号：US08525290B2

公开(公告)日：2013-09-03

申请号：US13168753

申请日：2011-06-24

申请人： Erh-Kun Lai ,  Hsiang-Lan Lung ,  Edward Kiewra

发明人： Erh-Kun Lai ,  Hsiang-Lan Lung ,  Edward Kiewra

IPC分类号： H01L21/70

CPC分类号： H01L27/1021 ,  H01L27/101

摘要： A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.

摘要翻译： 存储器件包括一个存取器件，它包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域。 第一掺杂半导体区域和第二掺杂半导体区域均形成在单晶半导体本体中，并且在它们之间限定p-n结。 第一和第二掺杂半导体区域被实现在形成在单晶半导体本体中的隔离的平行脊中。 每个山脊都是锯齿状的，扇形界定半岛; 第一掺杂半导体区域占据岛的下部和脊的上部，并且第二掺杂半导体区占据岛的上部，从而在岛内限定p-n结。

公开(公告)号：US08203187B2

公开(公告)日：2012-06-19

申请号：US12705158

申请日：2010-02-12

申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

IPC分类号： H01L29/76

CPC分类号： G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US08586960B2

公开(公告)日：2013-11-19

申请号：US12142239

申请日：2008-06-19

申请人： Thomas Happ ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

发明人： Thomas Happ ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

IPC分类号： H01L29/06

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

公开(公告)号：US20090200534A1

公开(公告)日：2009-08-13

申请号：US12027675

申请日：2008-02-07

申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

IPC分类号： H01L47/00 ,  H01L21/36

CPC分类号： H01L27/24 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02667 ,  H01L27/1021 ,  H01L29/8613

摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

摘要翻译： 本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

公开(公告)号：US20090185411A1

公开(公告)日：2009-07-23

申请号：US12017581

申请日：2008-01-22

申请人： Thomas Happ ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

发明人： Thomas Happ ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

IPC分类号： G11C11/00 ,  H01L21/06

CPC分类号： H01L27/24 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72

摘要： The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.

摘要翻译： 集成电路包括耦合到第一金属线的第一金属线和第一二极管。 集成电路包括耦合到第一二极管的第一电阻率变化材料和耦合到第一电阻率变化材料的第二金属线。

公开(公告)号：US20090176354A1

公开(公告)日：2009-07-09

申请号：US11970100

申请日：2008-01-07

申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung

发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung

IPC分类号： H01L21/20

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/02689 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/8613

摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.

摘要翻译： 本发明在一个实施例中提供了一种制造PN结的方法，该方法包括提供单晶衬底; 在单晶基板上形成绝缘层; 通过所述绝缘层形成通孔以提供所述单晶衬底的暴露部分; 在单晶衬底的至少暴露部分上形成非晶Si; 将至少一部分非晶Si转化为单晶Si; 并在单晶Si中形成掺杂区。 在一个实施例中，本发明的二极管与存储器件集成。