公开(公告)号：US10326211B2

公开(公告)日：2019-06-18

申请号：US15453327

申请日：2017-03-08

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Adel Elsherbini

IPC: H01Q1/38 ,  H01Q21/00 ,  H01Q21/22 ,  H01L23/00 ,  H01Q21/06 ,  H01Q23/00 ,  G06K19/077

Abstract: Embodiments described herein generally relate to phased array antenna systems or packages and techniques of making and using the systems and packages. A phased array antenna package may include a distributed phased array antenna comprising (1) a plurality of antenna sub-arrays, which may each include a plurality of antennas, (2) a plurality of Radio Frequency Dies (RFDs), each of the RFDs located proximate and electrically coupled by a trace of a plurality of traces to a corresponding antenna sub-array of the plurality of antenna sub-arrays, and (3) wherein each trace of the plurality of traces configured to electrically couple an antenna of the plurality of antennas to the RFD located proximate the antenna, wherein each trace of the plurality of traces is configured to transmit millimeter wave (mm-wave) radio signals, and wherein the plurality of traces are each of a substantially uniform length.

公开(公告)号：US09788581B2

公开(公告)日：2017-10-17

申请号：US14865440

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel Elsherbini ,  Sasha Oster ,  Braxton Lathrop ,  Nadine L. Dabby ,  Feras Eid

IPC: G06F3/01 ,  H05K7/00 ,  A41D1/00 ,  G06F1/16 ,  H05K1/03 ,  H05K1/02

CPC classification number: A41D1/002 ,  G06F1/163 ,  H05K1/0283 ,  H05K1/0296 ,  H05K1/038 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2201/10098 ,  H05K2201/10151

Abstract: Some forms relate to an electronic system that includes a textile. The electronic system includes a stretchable body that includes an integrated circuit that is configured to compute and communicate with an external device, wherein the stretchable body further includes at least one of (i) a power source that provides power to at least one of the electronic components; (ii) at least one sensor; (iii) a sensing node that receives signals from each sensor and sends signals to the integrated circuit; and (iv) an antenna that is configured to send and receive signals to and from the integrated circuit and the external device; and a textile attached to the stretchable body.

公开(公告)号：US09635764B2

公开(公告)日：2017-04-25

申请号：US14866648

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Shipeng Qiu ,  Shawna Liff ,  Kayleen L Helms ,  Joshua D Heppner ,  Adel Elsherbini ,  Johanna Swan ,  Gary M. Barnes

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/32 ,  H05K1/14 ,  H05K3/36 ,  H05K3/22 ,  H05K3/30 ,  H05K3/00

CPC classification number: H05K1/189 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/036 ,  H05K1/144 ,  H05K3/0014 ,  H05K3/22 ,  H05K3/303 ,  H05K3/326 ,  H05K3/361 ,  H05K2201/0133 ,  H05K2201/0308 ,  H05K2201/041 ,  H05K2201/047 ,  H05K2201/057 ,  H05K2201/10007 ,  H05K2201/10128 ,  H05K2203/10 ,  H05K2203/104 ,  H05K2203/105 ,  H05K2203/1105 ,  H05K2203/1194

Abstract: An integrated circuit that includes a substrate having a shape memory material (SMM), the SMM is in a first deformed state and has a first crystallography structure and a first configuration, the SMM is able to be deformed from a first configuration to a second configuration, the SMM changes to a second crystallography structure and deforms back to the first configuration upon receiving energy, the SMM returns to the first crystallography structure upon receiving a different amount of energy; and an electronic component attached to substrate. In other forms, the SMM is in a first deformed state and has a first polymeric conformation and a first configuration, the SMM changes from a first polymeric conformation to a second polymeric conformation and be deformed from a first configuration to a second configuration, the SMM changes returns to the first polymeric conformation and deforms back to the first configuration upon receiving energy.

公开(公告)号：US20250112216A1

公开(公告)日：2025-04-03

申请号：US18478937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Qiang Yu ,  Georgios C. Dogiamis ,  Said Rami ,  Adel Elsherbini

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more thick gate oxide transistors, group III-V transistors, varactors, or electrostatic discharge protection devices. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

公开(公告)号：US20250112196A1

公开(公告)日：2025-04-03

申请号：US18478843

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna Swan ,  Adel Elsherbini ,  Thomas L. Sounart ,  Tushar Kanti Talukdar ,  Brandon M. Rawlings ,  Kimin Jun ,  Andrey Vyatskikh ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/373 ,  H01L23/38 ,  H01L23/433 ,  H01L23/538 ,  H10N19/00

Abstract: An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.

公开(公告)号：US20250112177A1

公开(公告)日：2025-04-03

申请号：US18374516

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Thomas Sounart ,  Yi Shi ,  Michael Baker ,  Adel Elsherbini ,  Kimin Jun ,  Xavier Brun ,  Wenhao Li

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/786

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.

公开(公告)号：US20250112067A1

公开(公告)日：2025-04-03

申请号：US18478963

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Thomas L. Sounart ,  Feras Eid ,  Tushar Kanti Talukdar ,  Adel Elsherbini ,  Carlos Bedoya Arroyave ,  Johanna Swan

IPC: H01L21/67 ,  H01L21/56 ,  H01L21/683 ,  H01L21/762

Abstract: In one embodiment, a selective transfer process includes forming a layer of integrated circuit (IC) components on a first substrate. The method also includes dispensing liquid droplets into a subset of a plurality of areas of a second substrate, where the areas of the second substrate are defined by hydrophobic lines patterned to match a layout of the IC components on the first substrate. The method further includes partially bonding the first substrate to the second substrate, where a subset of the IC components on the first substrate are bonded to the liquid droplets on the second substrate (e.g., via capillary forces), and separating the first substrate from the second substrate. When the first substrate is separated from the second substrate, the subset of IC components is separated from the first substrate and remain on the second substrate.

公开(公告)号：US20250108459A1

公开(公告)日：2025-04-03

申请号：US18478770

申请日：2023-09-29

Applicant: INTEL CORPORATION

Inventor： Andrey Vyatskikh ,  Feras Eid ,  Tushar Kanti Talukdar ,  Kimin Jun ,  Thomas L. Sounart ,  Jeffery D. Bielefeld ,  Grant M. Kloster ,  Carlos Bedoya Arroyave ,  Golsa Naderi ,  Adel Elsherbini

IPC: B23K26/40 ,  B23K26/53 ,  B23K101/40 ,  B23K103/00

Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.

公开(公告)号：US20240063143A1

公开(公告)日：2024-02-22

申请号：US17891690

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Lance C. Hibbeler ,  Omkar Karhade ,  Chytra Pawashe ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Wenhao Li

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/3511

Abstract: Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.

公开(公告)号：US20240063142A1

公开(公告)日：2024-02-22

申请号：US17891666

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Botao Zhang ,  Yi Shi ,  Haris Khan Niazi ,  Feras Eid ,  Nagatoshi Tsunoda ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Omkar Karhade ,  Shawna Liff ,  Jiraporn Seangatith

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/367 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/486 ,  H01L21/565 ,  H01L25/0655 ,  H01L25/50

Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.