公开(公告)号：US20220199833A1

公开(公告)日：2022-06-23

申请号：US17133197

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Uygar Avci ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Sou-Chi Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1159 ,  H01L29/51

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

公开(公告)号：US11316027B2

公开(公告)日：2022-04-26

申请号：US16833375

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Nazila Haratipour ,  Tanay Gosavi ,  I-Cheng Tung ,  Seung Hoon Sung ,  Ian Young ,  Jack Kavalieros ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/24 ,  H01L29/92

Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.

公开(公告)号：US20210167073A1

公开(公告)日：2021-06-03

申请号：US16700782

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Uygar E. Avci

IPC: H01L27/1159 ,  G11C11/22 ,  G11C5/06 ,  H01L27/11507 ,  H01L29/78 ,  H01L29/66 ,  H01L49/02

Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.

公开(公告)号：US20200286687A1

公开(公告)日：2020-09-10

申请号：US16296085

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Nazila Haratipour ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L27/108 ,  H01L49/02 ,  G11C11/22

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

公开(公告)号：US20200212532A1

公开(公告)日：2020-07-02

申请号：US16238421

申请日：2019-01-02

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01P7/10 ,  H01L27/02 ,  H01L49/02 ,  H01P11/00

Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.

公开(公告)号：US20250112122A1

公开(公告)日：2025-04-03

申请号：US18477906

申请日：2023-09-29

Applicant: INTEL CORPORATION

Inventor： Kevin P. O'Brien ,  Paul Gutwin ,  David L. Kencke ,  Mahmut Sami Kavrik ,  Daniel Chanemougame ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Uygar E. Avci ,  Tristan A. Tronic ,  Chelsey Dorow ,  Andrey Vyatskikh ,  Rachel A. Steinhardt ,  Chia-Ching Lin ,  Chi-Yin Cheng ,  Yu-Jin Chen ,  Tyrone Wilson

IPC: H01L23/48 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/18 ,  H01L29/423 ,  H01L29/78

Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.

公开(公告)号：US20250107147A1

公开(公告)日：2025-03-27

申请号：US18476248

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar E. Avci ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Jack T. Kavalieros ,  Chia-Ching Lin ,  Matthew V. Metz ,  Wouter Mortelmans ,  Carl Hugo Naylor ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carly Rogan ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Andrey Vyatskikh

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

公开(公告)号：US20250006434A1

公开(公告)日：2025-01-02

申请号：US18883126

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H10B12/00

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

公开(公告)号：US20240222484A1

公开(公告)日：2024-07-04

申请号：US18092152

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Chelsey Dorow ,  Kirby Maxey ,  Carl H. Naylor ,  Tao Chu ,  Guowei Xu ,  Uygar Avci ,  Feng Zhang ,  Ting-Hsiang Hung ,  Ande Kitamura ,  Mahmut Sami Kavrik

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.

公开(公告)号：US20240222482A1

公开(公告)日：2024-07-04

申请号：US18091192

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Rachel Steinhardt ,  Chelsey Dorow ,  Carl H. Naylor ,  Kirby Maxey ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Scott Clendenning ,  Tristan Tronic ,  Mahmut Sami Kavrik ,  Ande Kitamura

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: Devices, transistor structures, systems, and techniques are described herein related to field effect transistors having a doping layer on metal chalcogenide nanoribbons outside of the channel region. The doping layer is a metal oxide that shifts the electrical characteristics of the nanoribbons and is formed by depositing a metal and oxidizing the metal by exposure to ozone and ultraviolet light.