公开(公告)号：US20190155160A1

公开(公告)日：2019-05-23

申请号：US16252427

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC: G03F7/20 ,  H01L21/311 ,  H01L21/027 ,  H01J37/317

CPC classification number: G03F7/2037 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The first and second columns of openings together form an array having a pitch in the first direction. A scan direction of the BAA is along a second direction, orthogonal to the first direction. The pitch of the array corresponds to half of a minimal pitch layout of a target pattern of lines for orientation parallel with the second direction.

公开(公告)号：US20180219012A1

公开(公告)日：2018-08-02

申请号：US15747692

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Donald W. NELSON ,  Stephen M. CEA

IPC: H01L27/108

CPC classification number: H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/1087

Abstract: Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.

公开(公告)号：US20180143526A1

公开(公告)日：2018-05-24

申请号：US15873782

申请日：2018-01-17

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC: G03F1/20 ,  H01J37/04 ,  H01J37/302 ,  H01J37/317 ,  G03F7/20 ,  H01L21/768

CPC classification number: G03F1/20 ,  G03F7/203 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/76802

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA includes three distinct aperture arrays of different pitch.

公开(公告)号：US20170077389A1

公开(公告)日：2017-03-16

申请号：US15122911

申请日：2014-06-16

Applicant: INTEL CORPORATION

Inventor： Donald W. NELSON ,  M Clair WEBB ,  Patrick MORROW ,  Kimin JUN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0694 ,  H01L27/101 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.

Abstract translation: 一种方法，包括在包括多个电路装置的集成电路装置层的相对侧上形成多个第一互连和多个第二互连，其中形成多个第一互连中的一个和多个第二互连包括嵌入存储器件 其中。 一种装置，包括在包括多个电路装置的集成电路装置层的相对侧上包括多个第一互连和多个第二互连的基板，其中多个第一互连和多个第二互连中的一个包括存储装置 嵌入其中。

公开(公告)号：US20170076905A1

公开(公告)日：2017-03-16

申请号：US15122400

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC: H01J37/04 ,  G03F7/20 ,  H01L21/768 ,  G03F1/20 ,  H01J37/317 ,  H01J37/302

CPC classification number: G03F1/20 ,  G03F7/203 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/76802

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA includes three distinct aperture arrays of different pitch.

Abstract translation: 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，描述了用于电子束工具的遮光器孔径阵列（BAA）。 BAA包括三个不同节距的不同孔径阵列。