公开(公告)号：US12288746B2

公开(公告)日：2025-04-29

申请号：US16727747

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

公开(公告)号：US12164319B2

公开(公告)日：2024-12-10

申请号：US17128073

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Sathya Narasimman Tiagaraj ,  Gerald Pasdast ,  Edward Burton

IPC: G05F1/575 ,  G06F1/26

Abstract: A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

公开(公告)号：US20230258716A1

公开(公告)日：2023-08-17

申请号：US18129315

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Debendra Das Sharma ,  Gerald Pasdast ,  Zuogo Wu ,  Narasimha Lanka ,  Lakshmipriya Seshan

IPC: G01R31/3183 ,  G01R31/317

CPC classification number: G01R31/318314 ,  G01R31/31712 ,  G01R31/31718

Abstract: Techniques to perform semiconductor testing are described. Test equipment may test a chiplet for compliance with a semiconductor specification. A test device may connect to a test package with a model chiplet and a device under test (DUT) chiplet. The model chiplet may comprise a known good model (KGM) of the semiconductor specification. The test device may use the model chiplet to test the DUT chiplet. Other embodiments are described and claimed.

公开(公告)号：US11652059B2

公开(公告)日：2023-05-16

申请号：US17536804

申请日：2021-11-29

Applicant: INTEL CORPORATION

Inventor： Adel Elsherbini ,  Shawna Lift ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US11586579B2

公开(公告)日：2023-02-21

申请号：US17513795

申请日：2021-10-28

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20220327276A1

公开(公告)日：2022-10-13

申请号：US17844356

申请日：2022-06-20

Applicant: Intel Corporation

Inventor： Lakshmipriya Seshan ,  Gerald Pasdast ,  Peipei Wang ,  Narasimha Lanka ,  Swadesh Choudhary ,  Zuoguo Wu ,  Debendra Das Sharma

IPC: G06F30/398 ,  G06F30/347 ,  G06F30/392

Abstract: In one embodiment, an apparatus includes a first die comprising: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry, where the die-to-die adapter is to receive first information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter. The physical layer circuitry is configured to receive and output the first information to a second die via an interconnect and comprises: a first plurality of transmitters to transmit data via a first plurality of data lanes; and at least one redundant transmitter. The physical layer circuitry may be configured to remap a first data lane of the first plurality of data lanes to the at least one redundant transmitter. Other embodiments are described and claimed.

公开(公告)号：US20220318111A1

公开(公告)日：2022-10-06

申请号：US17844348

申请日：2022-06-20

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

IPC: G06F11/263 ,  G06F13/42

Abstract: In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

公开(公告)号：US11270947B2

公开(公告)日：2022-03-08

申请号：US16698557

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US12159840B2

公开(公告)日：2024-12-03

申请号：US16910023

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Juan Zeng ,  Peipei Wang ,  Ahmad Siddiqui ,  Lakshmipriya Seshan

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/538

Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

公开(公告)号：US20240329129A1

公开(公告)日：2024-10-03

申请号：US18537076

申请日：2023-12-12

Applicant: Intel Corporation

Inventor： Sridhar Muthrasanallur ,  Debendra Das Sharma ,  Swadesh Choudhary ,  Gerald Pasdast ,  Peter Onufryk

IPC: G01R31/317 ,  G06F11/27 ,  G06F13/42

CPC classification number: G01R31/31705 ,  G06F11/27 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.