公开(公告)号：US20190146335A1

公开(公告)日：2019-05-16

申请号：US16097960

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20180086627A1

公开(公告)日：2018-03-29

申请号：US15573342

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Kevin LAI LIN ,  Chytra PAWASHE ,  Raseong KIM ,  Ian A. YOUNG ,  Kanwal Jit SINGH ,  Robert L. BRISTOL

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/092 ,  B81B2207/094 ,  B81B2207/095 ,  B81C1/00246 ,  B81C1/00301 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742 ,  B81C2203/0771 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829

Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

公开(公告)号：US20170345643A1

公开(公告)日：2017-11-30

申请号：US15529482

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Todd R. YOUNKIN ,  Michael J. LEESON ,  James M. BLACKWELL ,  Ernisse S. PUTNA ,  Marie KRYSAK ,  Rami HOURANI ,  Eungnak HAN ,  Robert L. BRISTOL

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/0271 ,  G03F7/0035 ,  G03F7/094 ,  G03F7/095 ,  G03F7/115 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L2224/16225

Abstract: Photodefinable alignment layers for chemical assisted patterning and approaches for forming photodefinable alignment layers for chemical assisted patterning are described. An embodiment of the invention may include disposing a chemically amplified resist (CAR) material over a hardmask that includes a switch component. The CAR material may then be exposed to form exposed resist portions. The exposure may produces acid in the exposed portions of the CAR material that interact with the switch component to form modified regions of the hardmask material below the exposed resist portions.

公开(公告)号：US20230369207A1

公开(公告)日：2023-11-16

申请号：US17743948

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Clifford J. ENGEL ,  Robert L. BRISTOL ,  Richard H. LIVENGOOD ,  Mahesh TANNIRU ,  Akshit PEER ,  Mauro J. KOBRINSKY ,  Kevin Lai LIN

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a first conductive line and a second conductive line in a first dielectric layer, the second conductive line laterally spaced apart from the first conductive line. The integrated circuit structure also includes a first conductive via and a second conductive via in a second dielectric layer, the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via vertically over and connected to the first conductive line, and the second conductive via vertically over but separated from the second conductive line.

公开(公告)号：US20220262722A1

公开(公告)日：2022-08-18

申请号：US17735006

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20220229364A1

公开(公告)日：2022-07-21

申请号：US17712953

申请日：2022-04-04

Applicant: Intel Corporation

Inventor： Marie KRYSAK ,  James M. BLACKWELL ,  Robert L. BRISTOL ,  Florian GSTREIN

IPC: G03F7/004 ,  G03F7/20

Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.

公开(公告)号：US20220216065A1

公开(公告)日：2022-07-07

申请号：US17701367

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Marie KRYSAK ,  James M. BLACKWELL ,  Florian GSTREIN ,  Kent N. FRASURE

IPC: H01L21/311 ,  G03F7/004 ,  G03F7/039 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US20190318958A1

公开(公告)日：2019-10-17

申请号：US16317015

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Kevin L. LIN ,  James M. BLACKWELL ,  Rami HOURANI ,  Eungnak HAN

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

公开(公告)号：US20190302615A1

公开(公告)日：2019-10-03

申请号：US16316594

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Marie KRYSAK ,  James M. BLACKWELL ,  Robert L. BRISTOL ,  Florian GSTREIN

IPC: G03F7/004 ,  G03F7/20

Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.

公开(公告)号：US20190206733A1

公开(公告)日：2019-07-04

申请号：US16093076

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert L. BRISTOL ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.