公开(公告)号：US20170317187A1

公开(公告)日：2017-11-02

申请号：US15528793

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Marc C. FRENCH ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/66742 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.

公开(公告)号：US20160276438A1

公开(公告)日：2016-09-22

申请号：US15036406

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

Abstract translation: 公开了用于在具有多纵横比掩模的不同基板上形成无缺陷半导体结构的技术。 多纵横比掩模包括形成在基板上的第一，第二和第三层。 第二层分别具有比第一和第三层中的第一开口和第三开口更宽的第二开口。 所有三个开口沿着共同的中心轴线居中。 半导体材料从衬底的顶表面生长并横向放置在第二开口内的第一层的顶表面上。 通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内并垂直于第三开口下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

公开(公告)号：US20190304896A1

公开(公告)日：2019-10-03

申请号：US16462889

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines

公开(公告)号：US20190148512A1

公开(公告)日：2019-05-16

申请号：US16099418

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Chandra S. MOHAPATRA ,  Sanaz K. GARDNER ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/768

Abstract: An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body include a contact surface between opposing sidewalls and the contact surface includes a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; and forming a gate stack on the body in the channel region.

公开(公告)号：US20190067081A1

公开(公告)日：2019-02-28

申请号：US16083859

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Seung Hoon SUNG

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L29/20 ,  H01L33/20 ,  H01L33/44

Abstract: A method of fabricating a wafer is disclosed. The method includes forming a protective layer on a device side and a non-device side of a substrate of the wafer. The method further includes removing the protective layer from a center portion of the device side of the substrate while retaining the protective layer in an edge portion of the substrate. The method also includes forming semiconductor layer in the center portion of the device side of the substrate while the protective layer is in the edge portion of the substrate.

公开(公告)号：US20180158957A1

公开(公告)日：2018-06-07

申请号：US15575111

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Sanaz K. GARDNER

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

公开(公告)号：US20170323963A1

公开(公告)日：2017-11-09

申请号：US15528802

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/66818

Abstract: An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.

公开(公告)号：US20170236928A1

公开(公告)日：2017-08-17

申请号：US15499774

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L21/30612 ,  H01L21/30617 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

公开(公告)号：US20160308041A1

公开(公告)日：2016-10-20

申请号：US15036780

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Robert S. CHAU ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Ravi PILLARISETTY

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L29/32 ,  H01L29/34 ,  H01L29/08 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/785 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transitors and other transistors can form.

Abstract translation: 公开了在半导体衬底上形成GaN晶体管的技术。 在半导体衬底的顶部形成绝缘层。 填充有包含III-V族半导体材料的沟槽材料的沟槽通过绝缘层形成并延伸到半导体衬底中。 含有缺陷密度低于沟槽材料的III-V材料的沟道结构直接形成在绝缘层的顶部并且与沟槽相邻。 在沟道结构的相对侧上的源极和漏极形式，以及在沟道结构上形成栅极。 半导体衬底形成可以形成GaN移动器和其它晶体管的平面。

公开(公告)号：US20160056244A1

公开(公告)日：2016-02-25

申请号：US14779257

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Benjamin CHU-KUNG ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/04 ,  H01L21/324 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684

Abstract: A fin over an insulating layer on a substrate having a first crystal orientation is modified to form a surface aligned along a second crystal orientation. A device layer is deposited over the surface of the fin aligned along the second crystal orientation.

Abstract translation: 在具有第一晶体取向的基板上的绝缘层上的鳍被修改以形成沿着第二晶体取向对准的表面。 器件层沉积在沿着第二晶体取向对准的鳍片的表面上。