公开(公告)号：US20210098422A1

公开(公告)日：2021-04-01

申请号：US16586145

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

公开(公告)号：US20190050040A1

公开(公告)日：2019-02-14

申请号：US16146463

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G06F1/32

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example multi-die package includes a computer processor unit (CPU) die, a memory die stacked in vertical alignment with the CPU die, and artificial intelligence (AI) architecture circuitry to infer a workload for at least one of the CPU die or the memory die. The AI architecture circuitry is to manage power consumption of at least one of the CPU die or the memory die based on the inferred workload.

公开(公告)号：US08872225B2

公开(公告)日：2014-10-28

申请号：US13722824

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/785

Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.

Abstract translation: 一个实施例使用非常薄的层纳米结构（例如，Si或SiGe鳍）作为模板来生长晶体，非晶格匹配的外延（EPI）层。 在一个实施方案中，纳米结构和EPI层之间的体积比使得EPI层比纳米结构厚。 在一些实施例中，在纳米结构和EPI之间包括非常薄的桥接层。 一个实施例包括一个CMOS器件，其中覆盖翅片（或一旦被覆盖的翅片）的EPI层彼此相反地极化。 一个实施例包括一个CMOS器件，其中覆盖翅片（或一旦被覆盖的翅片）的EPI层与覆盖翅片（或一旦被覆盖的翅片）的桥接层相反地偏振。 因此，从EPI层转移到纳米结构（剩下的存在或去除）的缺陷中公开了各种实施例。 本文描述了其它实施例。

公开(公告)号：US20250006495A1

公开(公告)日：2025-01-02

申请号：US18216485

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Allen Gardiner ,  Nikhil Mehta ,  Shu Zhou ,  Travis LaJoie ,  Shem Ogadhoh ,  Akash Garg ,  Van Le ,  Christopher Pelto ,  Bernhard Sell

IPC: H01L21/033 ,  H10B12/00

Abstract: A method for manufacturing integrated circuit (IC) devices includes forming first and second mask patterns with overlapping and non-overlapping features. Non-overlapping features may be removed before etching a target material layer. A third mask pattern may be formed from the overlapping features and used to etch a target material layer. The third mask pattern may be employed to make regular arrays of substantially rectangular structures.
An IC device may include an IC die, an array of structures on a layer of the IC die, and multiple groups of parallel stripes of indentations or depressions in the layer. The structures may each include a transistor and a capacitor.

公开(公告)号：US20240332285A1

公开(公告)日：2024-10-03

申请号：US18129702

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Abhishek Anil Sharma ,  Sudipto Naskar ,  Kalyan C. Kolluru ,  Chu-Hsin Liang ,  Bashir Uddin Mahmud ,  Van Le

IPC: H01L27/02 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786 ,  H01L29/872 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/0296 ,  H01L29/6603 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/872 ,  H02H9/046

Abstract: An integrated circuit device comprising a resistor formed on a non-crystalline substrate, the resistor comprising a gate electrode; a gate dielectric in contact with the gate electrode; a source electrode and a drain electrode; and a thin film transistor TFT channel material coupled between the source electrode and the drain electrode.

公开(公告)号：US20240234579A1

公开(公告)日：2024-07-11

申请号：US18444520

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L29/66 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US11843058B2

公开(公告)日：2023-12-12

申请号：US17516569

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11694986B2

公开(公告)日：2023-07-04

申请号：US17500824

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Patrick Morrow ,  Johanna Swan ,  Shawna Liff ,  Mauro Kobrinksy ,  Van Le ,  Gerald Pasdast

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/24147 ,  H01L2224/24155

Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

公开(公告)号：US11257956B2

公开(公告)日：2022-02-22

申请号：US15942175

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Gilbert Dewey ,  Van Le ,  Jack Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/08 ,  H01L21/425 ,  H01L29/66 ,  H01L29/423

Abstract: A thin film transistor (TFT) device is provided, where the TFT may include a source and a drain, a gate stack, and a semiconductor body. The gate stack may include a gate dielectric structure and a gate electrode, and the gate stack may be between the source and the drain. A first section of the semiconductor body may be adjacent to at least a section of the gate stack. A spacer may be between the gate stack and the source, where the spacer may be on the semiconductor body, and where a second section of the semiconductor body underneath the spacer may comprise dopants.

公开(公告)号：US20210375830A1

公开(公告)日：2021-12-02

申请号：US17399185

申请日：2021-08-11

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.