公开(公告)号：US20180331051A1

公开(公告)日：2018-11-15

申请号：US15776021

申请日：2015-12-22

Applicant: Georgios C. DOGLAMIS ,  Telesphor KAMGAING ,  Eric J. LI ,  Javier A. FALCON ,  INTEL CORPORATION

Inventor： Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Eric J. LI, Sr. ,  Javier A. FALCON ,  Yoshihiro TOMITA ,  Vijay K. NAIR ,  Shawna M. LIFF

IPC: H01L23/66 ,  H01L23/552 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31

Abstract: Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first die. In one example, the second die is formed with compound semiconductor materials. The microelectronic device includes a substrate that is coupled to the first die with a plurality of electrical connections. The substrate including an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20170288639A1

公开(公告)日：2017-10-05

申请号：US15088830

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Feras EID ,  Baris BICEN ,  Telesphor KAMGAING ,  Vijay K. NAIR ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN ,  Valluri R. RAO

IPC: H03H9/30 ,  H03H9/13

Abstract: Embodiments of the invention include a waveguide structure that includes a first piezoelectric transducer that is positioned in proximity to a first end of a cavity of an organic substrate. The first piezoelectric transducer receives an input electrical signal and generates an acoustic wave to be transmitted with a transmission medium. A second piezoelectric transducer is positioned in proximity to a second end of the cavity. The second piezoelectric transducer receives the acoustic wave from the transmission medium and generates an output electrical signal.

公开(公告)号：US20170283249A1

公开(公告)日：2017-10-05

申请号：US15088982

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Feras EID ,  Adel A. ELSHERBINI ,  Vijay K. NAIR ,  Telesphor KAMGAING ,  Valluri R. RAO ,  Johanna M. SWAN

IPC: B81B7/00

CPC classification number: B81C1/0015 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04

Abstract: Embodiments of the invention include a switching device that includes an electrode, a piezoelectric material coupled to the electrode, and a movable structure (e.g., cantilever, beam) coupled to the piezoelectric material. The movable structure includes a first end coupled to an anchor of a package substrate having organic layers and a second released end positioned within a cavity of the package substrate.

公开(公告)号：US20180350772A1

公开(公告)日：2018-12-06

申请号：US15777040

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Vijay K. NAIR ,  Georgios C. DOGIAMIS ,  Telesphor KAMGAING

IPC: H01L25/065 ,  H01L23/66 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/66 ,  H01L24/16 ,  H01L25/065 ,  H01L25/105 ,  H01L2224/16225

Abstract: Embodiments of the invention include a microelectronic device that includes a transceiver coupled to a first substrate and a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. An interposer substrate can provide a spacing between the first and second substrates.

公开(公告)号：US20180316383A1

公开(公告)日：2018-11-01

申请号：US15771865

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Vijay K. NAIR

IPC: H04B1/44 ,  H04B1/401 ,  H01Q3/42 ,  H01Q21/22

CPC classification number: H04B1/44 ,  H01Q3/36 ,  H01Q3/42 ,  H01Q21/06 ,  H01Q21/22 ,  H01Q23/00 ,  H04B1/18 ,  H04B1/401 ,  H04B1/48

Abstract: Embodiments of the invention include a communication module that includes a die having a transceiver and a phase shifter die that is coupled to the die. The phase shifter includes a power combiner and splitter. The communication module also includes a substrate that is coupled to the phase shifter die. The substrate includes an antenna unit with steerable beam forming capability for transmitting and receiving communications.

公开(公告)号：US20180286840A1

公开(公告)日：2018-10-04

申请号：US15765992

申请日：2015-11-04

Applicant: Intel Corporation

Inventor： Vijay K. NAIR ,  Adel A. ELSHERBINI ,  Lakshman KRISHNAMURTHY ,  Johanna M. SWAN ,  Alexander ESSAIAN ,  Torrey W. FRANK

IPC: H01L25/16 ,  H01L23/498 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/162 ,  H01L21/568 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19105

Abstract: Embodiments are generally directed to three-dimensional small form factor system in package architecture. An embodiment of an apparatus includes a first package having a first side and an opposite second side, the first package including a plurality of embedded electronic components and one or more embedded via bars, each via bar including a plurality of through vias; and a second package having a first side and an opposite second side, the second package including a plurality of embedded electronic components, wherein a first side of the first package and a second side of second package are coupled together by a plurality of connections, including at least a first connection connecting the second package to a first component of the first package and a second connection connecting the second package to a first via bar of the one or more via bars.

公开(公告)号：US20180269190A1

公开(公告)日：2018-09-20

申请号：US15982787

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Vijay K. NAIR ,  Thorsten MEYER

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/162 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16505 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/15331 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3651 ,  H01L2224/81

Abstract: Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a second surface that is opposite from the first surface. One or more first electrical components that each have a solderable terminal that is oriented to face the first surface of the mold layer. The mold layer may also have one or more second electrical components that each have a second type of terminal that is oriented to face the second surface of the mold layer. Embodiments may also include one or more conductive through vias formed between the first surface of the mold layer and the second surface of the mold layer. Accordingly an electrical connection may be made from the second surface of the mold layer to the first electrical components that are oriented to face the first surface of the mold layer.

公开(公告)号：US20170288642A1

公开(公告)日：2017-10-05

申请号：US15088987

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Feras EID ,  Georgios C. DOGIAMIS ,  Valluri R. RAO ,  Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Telesphor KAMGAING ,  Vijay K. NAIR

IPC: H03H9/54 ,  H03H9/05 ,  B01D21/30 ,  H03H9/17

CPC classification number: H03H9/54 ,  H03H9/05 ,  H03H9/0542 ,  H03H9/17 ,  H03H9/173 ,  H03H9/2463 ,  H03H2009/02503 ,  H03H2009/155

Abstract: Embodiments of the invention include a filtering device that includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The piezoelectric filtering device expands and contracts laterally in a plane of an organic substrate in response to application of an electrical signal between the first and second electrodes.

公开(公告)号：US20170285695A1

公开(公告)日：2017-10-05

申请号：US15089001

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Vijay K. NAIR ,  Feras EID ,  Adel A. ELSHERBINI ,  Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Valluri R. RAO ,  Johanna M. SWAN

IPC: G06F1/18 ,  H03H9/54 ,  H03H9/56

CPC classification number: G06F1/18 ,  H03H9/0542 ,  H03H9/0557 ,  H03H9/542 ,  H03H9/545 ,  H03H9/56 ,  H03H9/587

Abstract: Embodiments of the invention include a piezoelectric package integrated filtering device that includes a film stack. In one example, the film stack includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The film stack is suspended with respect to a cavity of an organic substrate having organic material and the film stack generates an acoustic wave to be propagated across the film stack in response to an application of an electrical signal between the first and second electrodes.

公开(公告)号：US20170207170A1

公开(公告)日：2017-07-20

申请号：US15106761

申请日：2015-07-22

Applicant: INTEL CORPORATION

Inventor： Vijay K. NAIR ,  Chuan HU ,  Thorsten MEYER

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.