公开(公告)号：US20230064289A1

公开(公告)日：2023-03-02

申请号：US17445831

申请日：2021-08-25

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Ruilong Xie

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  H01L27/22 ,  H01F10/32 ,  G11C11/16

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a spin transfer torque (STT) magnetoresistive random access memory (MRAM) stack. The semiconductor structure may also include a spin orbit torque (SOT) MRAM stack vertically in series with the STT-MRAM. The SOT-MRAM stack may include a heavy metal spin hall effect rail configured to flip an SOT free-layer magnetic orientation in response to a horizontal signal through the heavy metal rail.

公开(公告)号：US11380843B2

公开(公告)日：2022-07-05

申请号：US16789502

申请日：2020-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tian Shen ,  Heng Wu ,  Kevin W. Brew ,  Jingyun Zhang

IPC: H01L45/00

Abstract: A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode over a substrate, constructing a PCM stack including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

公开(公告)号：US11282838B2

公开(公告)日：2022-03-22

申请号：US16946856

申请日：2020-07-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Dechao Guo ,  Junli Wang ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li ,  Chanro Park ,  Ruqiang Bao ,  Sung Dae Suk ,  Lan Yu ,  Heng Wu

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a top channel and a bottom channel, wherein the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers located on each side of the gate. A first spacer includes a dielectric material located between the plurality of vertically oriented channels. A second spacer includes a dielectric material located between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.

公开(公告)号：US11251280B2

公开(公告)日：2022-02-15

申请号：US16717204

申请日：2019-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Chen Zhang ,  Kangguo Cheng ,  Xin Miao ,  Lan Yu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: Forming a fin, where the fin includes a nanowire stack on a semiconductor substrate, where the nanowire stack includes a plurality of silicon layers and a plurality of silicon germanium layers stacked one on top of the other in an alternating fashion, removing a portion of the fin to form an opening and expose vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layer, and epitaxially growing a source drain region/structure in the opening from the exposed vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, where the source drain region/structure substantially fills the opening.

公开(公告)号：US11189725B2

公开(公告)日：2021-11-30

申请号：US16735788

申请日：2020-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Lan Yu ,  Alexander Reznicek ,  Junli Wang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: Semiconductor devices and methods of forming the same include forming a restraint structure over a channel fin, having an opening that is smaller than a top surface of the channel fin. A top semiconductor structure is grown from the top surface of the channel fin, with lateral growth of the semiconductor structure being limited by the restraint structure.

公开(公告)号：US11164791B2

公开(公告)日：2021-11-02

申请号：US16283995

申请日：2019-02-25

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Tenko Yamashita ,  Chen Zhang ,  Joshua M. Rubin

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/822 ,  H01L27/088

Abstract: A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure including one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower VTFET, an isolation layer, and a second semiconductor layer providing a vertical transport channel for an upper VTFET. The method also includes forming at least one vertical via in the stacked VTFET structure spaced apart from the one or more vertical fins. The method further includes forming at least one horizontal via extending from the vertical via to at least one source/drain region of at least one of the upper and lower VTFETs. The method further includes forming a contact liner in the horizontal via, forming a barrier layer on sidewalls of the vertical via and the contact liner, and forming a contact material over the barrier layer in the vertical via.

公开(公告)号：US20210296396A1

公开(公告)日：2021-09-23

申请号：US16823311

申请日：2020-03-18

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Julien Frougier ,  Bruce B. Doris ,  Chen Zhang ,  Ruilong Xie

IPC: H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L43/08 ,  G11C11/16 ,  G11C13/00

Abstract: A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.

公开(公告)号：US20210257547A1

公开(公告)日：2021-08-19

申请号：US16789502

申请日：2020-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tian Shen ,  Heng Wu ,  Kevin W. Brew ,  Jingyun Zhang

IPC: H01L45/00

Abstract: A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode over a substrate, constructing a PCM stack including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

公开(公告)号：US11094798B2

公开(公告)日：2021-08-17

申请号：US16441640

申请日：2019-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lan Yu ,  Xin Miao ,  Chen Zhang ,  Heng Wu ,  Kangguo Cheng

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/40 ,  H01L21/324 ,  H01L29/78

Abstract: An embodiment of the invention may include a method of forming a semiconductor structure, and the resulting semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include removing a portion of the layered stack that is not beneath the hardmask.

公开(公告)号：US20210159390A1

公开(公告)日：2021-05-27

申请号：US16692766

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Ruilong Xie ,  Heng Wu ,  Lan Yu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A memory structure, and a method for forming the same, includes a spin-orbit-torque electrode within a dielectric layer located above a substrate. The spin-orbit-torque electrode including a first conductive material, and a spin-orbit torque via is directly above the spin-orbit-torque electrode that includes a second conductive material. A magnetic tunnel junction pillar is directly above the spin-orbit torque via, and the spin-orbit-torque via contacting a center of a bottom surface of the magnetic-tunnel-junction pillar. A third conductive material is positioned directly below the bottom surface of the magnetic tunnel junction pillar on opposite sides of the spin-orbit torque via and directly above the spin-orbit-torque electrode. The third conductive material, the spin-orbit torque electrode and the spin-orbit torque via form a bottom spin-orbit torque electrode of the magnetic tunnel junction pillar.