公开(公告)号：US20240329339A1

公开(公告)日：2024-10-03

申请号：US18191273

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Changhua Liu ,  Hiroki Tanaka ,  Brandon C. Marin ,  Srinivas V. Pietambaram

IPC: G02B6/42 ,  G02B6/38

CPC classification number: G02B6/4228 ,  G02B6/3886 ,  G02B6/4239 ,  G02B6/4292

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a photonic integrated circuit (PIC) having a first surface having a channel and a first magnetic material; a fiber connector including a second surface with a second magnetic material; and a fiber physically coupled to the second surface of the fiber connector by an adhesive material; wherein the first surface of the PIC is coupled to the second surface of the fiber connector by the first and second magnetic materials with the fiber positioned in the channel.

公开(公告)号：US20240219655A1

公开(公告)日：2024-07-04

申请号：US18089916

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Bai Nie ,  Brandon C. Marin ,  Dingying Xu ,  Gang Duan ,  Hongxia Feng ,  Jeremy D. Ecton ,  Kristof Darmawikarta ,  Kyle Jordan Arrington ,  Srinivas Venkata Ramanuja Pietambaram ,  Xiaoying Guo ,  Yiqun Bai ,  Ziyin Lin

IPC: G02B6/42 ,  H01L21/48

CPC classification number: G02B6/4214 ,  H01L21/4803 ,  H01L23/49827

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240176085A1

公开(公告)日：2024-05-30

申请号：US18059074

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: G02B6/43 ,  G02B6/122 ,  G02B6/30

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/30

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is along a perimeter of the core; and a second optical component coupled to the first optical component, wherein the second optical component is optically coupled to the PIC by an optical pathway through the first optical component.

公开(公告)号：US20240128181A1

公开(公告)日：2024-04-18

申请号：US18047033

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/32 ,  H01L2924/15311

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.

公开(公告)号：US20240114627A1

公开(公告)日：2024-04-04

申请号：US17937894

申请日：2022-10-04

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Robert Alan May ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Brandon C. Marin

IPC: H05K3/06 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09

CPC classification number: H05K3/062 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H05K1/09 ,  H05K3/067 ,  H01L25/0652

Abstract: Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.

公开(公告)号：US20240114622A1

公开(公告)日：2024-04-04

申请号：US17956338

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Cary Kuliasha ,  Siddharth K. Alur ,  Jung Kyu Han ,  Beomseok Choi ,  Russell K. Mortensen ,  Andrew Collins ,  Haobo Chen ,  Brandon C. Marin

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L25/0655 ,  H05K3/0047 ,  H05K3/4644 ,  H05K2201/1003 ,  H05K2201/10674

Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.

公开(公告)号：US20240101413A1

公开(公告)日：2024-03-28

申请号：US17954522

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Oladeji Fadayomi ,  Oscar Ojeda

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0006 ,  B81C1/00095 ,  B81C1/00523 ,  B81C1/00611 ,  B81B2207/07 ,  B81C2201/0123

Abstract: Disclosed herein are microelectronics package architectures having self-aligned air gaps and methods of manufacturing the same. The microelectronics packages may include first and second substrates, first and second traces, and a photosensitive material. The first trace may be attached to the first substrate and comprise a first sidewall. The second trace may be attached to the first substrate and comprise a second sidewall. The second traced may be spaced a distance from the first trace with the second sidewall facing the first sidewall. First and second portions of the photosensitive material may be attached to the first and second sidewalls, respectively. The second substrate may be attached to the first and second traces. The first and second substrates and the first and second traces may form the air gap in between the first and second traces.

公开(公告)号：US20240006298A1

公开(公告)日：2024-01-04

申请号：US17855040

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Steve Cho ,  Marcel Arlan Wall ,  Onur Ozkan ,  Ali Lehaf ,  Yi Yang ,  Jason Scott Steill ,  Gang Duan ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Haifa Hariri ,  Bai Nie ,  Hiroki Tanaka ,  Kyle Mcelhinny ,  Jason Gamba ,  Venkata Rajesh Saranam ,  Kristof Darmawikarta ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/481 ,  H01L23/49838

Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.

公开(公告)号：US11791228B2

公开(公告)日：2023-10-17

申请号：US16380486

申请日：2019-04-10

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Darmawikarta ,  Roy Dittler ,  Jeremy Ecton ,  Darko Grujicic

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/488

CPC classification number: H01L23/3114 ,  H01L23/3128 ,  H01L23/488

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

公开(公告)号：US20230200119A1

公开(公告)日：2023-06-22

申请号：US17556768

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Kristof Darmawikarta

IPC: H01L51/52 ,  H01L51/56

CPC classification number: H01L51/5275 ,  H01L51/56 ,  H01L51/5237

Abstract: Disclosed herein are organic semiconductors using optical signaling on a microelectronics package and methods for manufacturing the same. The microelectronics packages may include a substrate, an acceptor, a donor, and a solder resist layer. The substrate may include a trace. The acceptor may be in electrical communication with the trace. The donor may be connected to the acceptor. The solder resist layer may be connected to the substrate and encapsulate a portion of at least the acceptor.