公开(公告)号：US20160170456A9

公开(公告)日：2016-06-16

申请号：US13626357

申请日：2012-09-25

Applicant: INTEL CORPORATION

Inventor： Siva G. Narendra ,  James W. Tschanz ,  Howard A. Wilson ,  Donald S. Gardner ,  Peter Hazucha ,  Gerhard Schrom ,  Tanay Karnik ,  Nitin Borkar ,  Vivek K. De ,  Shekhar Y. Borkar

IPC: G06F1/26 ,  G06F1/32 ,  H01L25/065

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  H01L23/34 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  Y02D10/126 ,  Y02D10/172

Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Abstract translation: 公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

公开(公告)号：US11031288B2

公开(公告)日：2021-06-08

申请号：US16252420

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Sujit Sharan ,  Ravindranath Mahajan ,  Stefan Rusu ,  Donald S. Gardner

IPC: H01L21/78 ,  H01L23/48 ,  H01L23/522 ,  H01L25/16 ,  H01L49/02 ,  H01L23/538

Abstract: Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

公开(公告)号：US10236209B2

公开(公告)日：2019-03-19

申请号：US14583015

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sujit Sharan ,  Ravindranath Mahajan ,  Stefan Rusu ,  Donald S. Gardner

IPC: H01L21/78 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02 ,  H01L23/538 ,  H01L23/522 ,  H01L27/08

Abstract: Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

公开(公告)号：US20180337402A1

公开(公告)日：2018-11-22

申请号：US15823451

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Zhaohui Chen ,  Donald S. Gardner ,  Bum Ki Moon ,  Yang Liu

IPC: H01M4/38 ,  H01M4/62 ,  H01M10/052 ,  H01M4/66 ,  H01M4/04 ,  H01M4/1395 ,  H01M4/134 ,  H01M4/02

CPC classification number: H01M4/386 ,  H01M4/0402 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/624 ,  H01M4/66 ,  H01M10/052 ,  H01M2004/027

Abstract: Amorphous silicon anode electrodes and devices for a rechargeable batteries having enhanced structural stabilities are provided. An amorphous silicon anode can include an electrically conductive substrate and an electrode layer deposited onto the substrate, where the electrode layer is comprised of one or more amorphous silicon structures, and the amorphous silicon structures have at least one dimension that is less than or equal to about 500 nm.

公开(公告)号：US09997290B2

公开(公告)日：2018-06-12

申请号：US14752180

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Hossein Alavi

IPC: H01F21/08 ,  H01F27/28 ,  H01F29/14 ,  H01F21/00 ,  H04B1/00 ,  H04B1/18 ,  H01F38/14 ,  H04B1/16 ,  H04B1/403

CPC classification number: H01F29/14 ,  H01F17/0033 ,  H01F21/00 ,  H01F29/146 ,  H01F38/14 ,  H01F2029/143 ,  H01F2038/143 ,  H04B1/005 ,  H04B1/1638 ,  H04B1/18 ,  H04B1/403

Abstract: Embodiments of a variable inductor and a communication device are generally described herein. The variable inductor may comprise a signal wire and a control wire to receive a direct current (DC) control current. The variable inductor may further comprise a magnetic material integrated with the signal wire and the control wire. When a DC control current applied to the control wires takes a first current value, an inductance between an input node and an output node on the signal wire may take a first inductance value. When the DC control current takes a second current value, the inductance between the input node and the output node may take a second inductance value.

公开(公告)号：US20170155131A1

公开(公告)日：2017-06-01

申请号：US15340750

申请日：2016-11-01

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Charles W. Holzwarth ,  Bum Ki Moon ,  Yang Liu ,  Priyanka Pande ,  Shanthi Murali ,  Nicolas Cirigliano ,  Zhaohui Chen

IPC: H01M4/36 ,  H01M4/587 ,  H01M4/48 ,  H01M4/38

CPC classification number: H01M4/366 ,  H01M4/38 ,  H01M4/386 ,  H01M4/387 ,  H01M4/483 ,  H01M4/485 ,  H01M4/587 ,  H01M4/62 ,  H01M2004/021 ,  H01M2004/027 ,  Y02E60/122 ,  Y02P70/54 ,  Y10T29/49108 ,  Y10T29/49115

Abstract: Electrodes, energy storage devices using such electrodes, and associated methods are disclosed. In an example, an electrode for use in an energy storage device can comprise porous disks comprising a porous material, the porous disks having a plurality of channels and a surface, the plurality of channels opening to the surface; and a structural material encapsulating the porous disks; where the structural material provides structural stability to the electrode during use.

公开(公告)号：US20160187282A1

公开(公告)日：2016-06-30

申请号：US14583373

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： Donald S. Gardner ,  Oguz H. Elibol

IPC: G01N27/30 ,  C23C16/02 ,  H05K3/30 ,  G01N27/49 ,  C23C16/32

CPC classification number: G01N27/308 ,  C12Q1/6869 ,  C23C16/02 ,  C23C16/325 ,  G01N27/3277 ,  G01N27/3278 ,  G01N27/48 ,  G01N27/49 ,  G01N33/5438 ,  H05K3/303 ,  H05K2203/06 ,  C12Q2527/125 ,  C12Q2535/122 ,  C12Q2565/607 ,  C12Q2565/629 ,  C12Q2565/631

Abstract: Disclosed herein is a device comprising an electrode pair comprising a first electrode and a second electrode; a nanogap channel; wherein a portion of the nanogap channel is sandwiched between the first electrode and the second electrode; wherein at least a portion of the first electrode directly faces at least a portion of the second electrode, across the nanogap channel; wherein the portion of the first electrode and the portion of the second electrode are exposed to an interior of the nanogap channel; and wherein the first electrode or the second electrode comprises doped diamond, silicon carbide or a combination thereof. Also disclosed herein is a method comprising forming on a carrier substrate a first material layer comprising doped diamond, silicon carbide or a combination thereof; bonding the first material layer onto an electrical circuit.

Abstract translation: 本文公开了一种包括电极对的装置，包括第一电极和第二电极; 纳米沟渠 其中所述纳米槽通道的一部分夹在所述第一电极和所述第二电极之间; 其中所述第一电极的至少一部分直接面对所述第二电极的至少一部分，穿过所述纳米槽通道; 其中所述第一电极的所述部分和所述第二电极的所述部分暴露于所述纳米隙通道的内部; 并且其中所述第一电极或所述第二电极包括掺杂的金刚石，碳化硅或其组合。 本文还公开了一种方法，包括在载体衬底上形成包含掺杂金刚石，碳化硅或其组合的第一材料层; 将第一材料层接合到电路上。

公开(公告)号：US20150187515A1

公开(公告)日：2015-07-02

申请号：US14644632

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Eric C. Hannah ,  Rong Chen ,  John Gustafson

IPC: H01G11/26 ,  H01G11/52 ,  H01G2/02 ,  H01G11/54

CPC classification number: H01G11/86 ,  H01G2/02 ,  H01G9/048 ,  H01G11/24 ,  H01G11/26 ,  H01G11/36 ,  H01G11/52 ,  H01G11/54 ,  H01L28/82 ,  Y02E60/13

Abstract: In one embodiment a charge storage device includes first (110) and second (120) electrically conductive structures separated from each other by a separator (130). At least one of the first and second electrically conductive structures includes a porous structure containing multiple channels (111, 121). Each one of the channels has an opening (112, 122) to a surface (115, 125) of the porous structure. In another embodiment the charge storage device includes multiple nanostructures (610) and an electrolyte (650) in physical contact with at least some of the nanostructures. A material (615) having a dielectric constant of at least 3.9 may be located between the electrolyte and the nanostructures.

Abstract translation: 在一个实施例中，电荷存储装置包括通过分离器（130）彼此分离的第一（110）和第二（120）导电结构。 第一和第二导电结构中的至少一个包括包含多个通道（111,121）的多孔结构。 每个通道具有到多孔结构的表面（115,125）的开口（112,122）。 在另一个实施方案中，电荷存储装置包括与至少一些纳米结构物理接触的多个纳米结构（610）和电解质（650）。 具有至少3.9的介电常数的材料（615）可以位于电解质和纳米结构之间。