公开(公告)号：US20240222506A1

公开(公告)日：2024-07-04

申请号：US18148871

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Hojoon Ryu ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Kevin P. O'Brien ,  John J. Plombon ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66969 ,  H01L29/7606

Abstract: An apparatus, comprising a field effect transistor comprising a ferroelectric material, a channel material comprising a transition metal and a chalcogen, a source and a drain coupled to the channel material, the source and drain comprising a conductive material.

公开(公告)号：US20240206348A1

公开(公告)日：2024-06-20

申请号：US18083493

申请日：2022-12-17

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li

IPC: H10N52/85 ,  G11C11/16 ,  H03K19/20 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10N52/85 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/20 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: In embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2D) transition metal dichalcogenide (TMD) materials (e.g., NbSe2 or MoTe2).

公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US20230284457A1

公开(公告)日：2023-09-07

申请号：US17688495

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Hai Li ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Punyashloka Debashis ,  Ian Alexander Young ,  Julien Sebot

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06

CPC classification number: H01L27/22 ,  H01L43/04 ,  H01L43/06

Abstract: In one embodiment, a first integrated circuit component, a second integrated circuit component, and an electrical interconnect coupling the first integrated circuit component and the second integrated circuit component. The interconnect comprises one or more spintronic logic devices.

公开(公告)号：US20230155550A1

公开(公告)日：2023-05-18

申请号：US17530250

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Gary A. Allen ,  Tanay A. Gosavi ,  Raseong Kim ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H03B5/36 ,  H03H9/17

CPC classification number: H03B5/36 ,  H03H9/178 ,  H03L7/099

Abstract: In one embodiment, a piezo-resistive resonator device includes one or more drive transistors with source and drain regions in a first well and a sense transistor with source and drain regions in a second well of opposite polarity than the first well. The gates of the drive and sense transistor are connected to a first direct current (DC) source. The drain region of the sense transistor is connected to a second DC source, and the source and drain regions of the drive transistor are connected to an alternating current (AC) source.

公开(公告)号：US20230100649A1

公开(公告)日：2023-03-30

申请号：US17485265

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by an insulating layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor and can be switched through the application of an input voltage to the MEMTJ that causes the magnetoelectric switching capacitor to switch states. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The magnetization orientation of a ferromagnetic free layer common to the MTJs is coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of the ferromagnetic free layer is based on the power supply voltage applied to the ferromagnetic reference layer of the MTJ having a magnetization orientation parallel to that of the ferromagnetic free layer.

公开(公告)号：US20240222475A1

公开(公告)日：2024-07-04

申请号：US18148617

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  John J. Plombon ,  Scott B. Clendenning ,  Mahendra DC

IPC: H01L29/66 ,  H01F10/12 ,  H01F10/193 ,  H01F10/32 ,  H10N52/01

CPC classification number: H01L29/66984 ,  H01F10/12 ,  H01F10/1933 ,  H01F10/329 ,  H10N52/01

Abstract: Technologies for high-performance magnetoelectric spin-orbit (MESO) logic structures are disclosed. In the illustrative embodiment, the spin-orbit coupling layer of a MESO logic structure is a high-entropy perovskite. The use of a high-entropy perovskite provides versatility through tunability, as there is a wide range of possible combinations. Additional layers of the MESO logic structure may also be perovskites, such as the magnetoelectric layer and ferromagnetic layer. The various perovskite layers may be epitaxially compatible, allowing for growth of high-quality layers.

公开(公告)号：US20240147867A1

公开(公告)日：2024-05-02

申请号：US17978145

申请日：2022-10-31

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dominique A. Adams ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  John J. Plombon ,  Ian Alexander Young

IPC: H10N50/10 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/85

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.

公开(公告)号：US20240113220A1

公开(公告)日：2024-04-04

申请号：US17958094

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Uygar E. Avci ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Jason C. Retasket ,  Shriram Shivaraman ,  Dominique A. Adams ,  Carly Rogan ,  Punyashloka Debashis ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Sudarat Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7606

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

公开(公告)号：US20240113212A1

公开(公告)日：2024-04-04

申请号：US17956296

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Hai Li ,  Arnab Sen Gupta ,  Gauri Auluck ,  I-Cheng Tung ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Punyashloka Debashis

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/465 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.