公开(公告)号：US20200212291A1

公开(公告)日：2020-07-02

申请号：US16236060

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sasikanth MANIPATRUNI ,  Tanay GOSAVI ,  Dmitri NIKONOV ,  Kaan OGUZ ,  Ian A. YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32 ,  H01L27/11 ,  G11C11/16 ,  G11C11/14

Abstract: A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.

公开(公告)号：US20190006417A1

公开(公告)日：2019-01-03

申请号：US16069122

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Mark L. DOCZY ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE

IPC: H01L27/22 ,  G11C11/16

Abstract: Approaches and structures for unipolar current switching in perpendicular magnetic tunnel junction (pMTJ) devices through reduced bi-polar coercivity are described. In an example, a memory array includes a plurality of bitlines and a plurality of select lines. The memory array also includes a plurality of memory elements located among and coupled to the plurality of bitlines and the plurality of select lines. Each of the plurality of memory elements includes a unipolar switching magnetic tunnel junction (MTJ) device and a select device.

公开(公告)号：US20180165065A1

公开(公告)日：2018-06-14

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Justin S. BROCKMAN ,  Juan G. ALZATE VINASCO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Satyarth SURI ,  Robert S. CHAU ,  Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV

IPC: G06F7/58 ,  H01L43/08 ,  H01L43/02

CPC classification number: G06F7/588 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.

公开(公告)号：US20170200884A1

公开(公告)日：2017-07-13

申请号：US15324589

申请日：2014-08-05

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Charles C. KUO ,  Anurag CHAUDHRY ,  Robert S. CHAU

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe configurations and techniques to increase interfacial anisotropy of magnetic tunnel junctions. In embodiments, a magnetic tunnel junction may include a cap layer, a tunnel barrier, and a magnetic layer disposed between the cap layer and the tunnel barrier. A buffer layer may, in some embodiments, be disposed between the magnetic layer and a selected one of the cap layer or the tunnel barrier. In such embodiments, the interfacial anisotropy of the buffer layer and the selected one of the cap layer or the tunnel barrier may be greater than an interfacial anisotropy of the magnetic layer and the selected one of the cap layer or the tunnel barrier. Other embodiments may be described and/or claimed.

公开(公告)号：US20230411443A1

公开(公告)日：2023-12-21

申请号：US18129258

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Chia-Ching LIN ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Sou-Chi CHANG ,  Sudarat LEE ,  Matthew V. METZ ,  Uygar E. AVCI ,  Scott B. CLENDENNING ,  Ian A. YOUNG

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L28/56 ,  H01L28/92 ,  H01L28/91 ,  H01L28/75 ,  H01L23/5223 ,  H01L23/5226 ,  H01L24/32 ,  H01L28/65 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/73204

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

公开(公告)号：US20230100505A1

公开(公告)日：2023-03-30

申请号：US17485238

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Rahul RAMAMURTHY ,  I-Cheng TUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.

公开(公告)号：US20230098594A1

公开(公告)日：2023-03-30

申请号：US17484949

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Kaan OGUZ ,  Sou-Chi CHANG ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Sudarat LEE

IPC: H01G4/30 ,  H01L49/02 ,  H01G4/08 ,  H01G4/35

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199839A1

公开(公告)日：2022-06-23

申请号：US17133599

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arnab SEN GUPTA ,  Urusa ALAAN ,  Justin WEBER ,  Charles C. KUO ,  Yu-Jin CHEN ,  Kaan OGUZ ,  Matthew V. METZ ,  Abhishek A. SHARMA ,  Prashant MAJHI ,  Brian S. DOYLE ,  Van H. LE

IPC: H01L29/872 ,  H01L27/07 ,  H01L29/47 ,  H01L29/22

Abstract: Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

公开(公告)号：US20220199756A1

公开(公告)日：2022-06-23

申请号：US17133105

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： I-Cheng TUNG ,  Kaan OGUZ ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Matthew V. METZ ,  Uygar E. AVCI

IPC: H01L49/02 ,  H01L23/522 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: Metal insulator metal capacitors or backend transistors having epitaxial oxides are described. In a first example, metal-insulator-metal (MIM) capacitor includes a first electrode plate. A capacitor dielectric is on the first electrode plate. The capacitor dielectric includes a single crystalline oxide material. A second electrode plate is on the capacitor dielectric, the second electrode plate having a portion over and parallel with the first electrode plate. In a second example, a transistor includes a gate electrode above a substrate. A gate dielectric above and on the gate electrode. The gate dielectric includes a single crystalline oxide material. A channel material layer is on the single crystalline oxide material. Source or drain contacts are on the channel material layer.

公开(公告)号：US20220199519A1

公开(公告)日：2022-06-23

申请号：US17129854

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  I-Cheng TUNG ,  Arnab SEN GUPTA ,  Ian A. YOUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Ashish Verma PENUMATCHA ,  Anandi ROY

IPC: H01L23/522 ,  H01L49/02

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. The first capacitor dielectric is or includes a perovskite high-k dielectric material. A second electrode plate is on the first capacitor dielectric and has a portion over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and has a portion over and parallel with the second electrode plate.