公开(公告)号：US20200051956A1

公开(公告)日：2020-02-13

申请号：US16100149

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Nitin DESHPANDE ,  Debendra MALLIK

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package is disclosed. The semiconductor package includes a package substrate, at least one bottom die coupled to the package substrate, at least one interposer coupled to the package substrate and a top die above the at least one bottom die and the at least one interposer and coupled to the at least one bottom die and the at least one interposer. The semiconductor package also includes a plurality of pillars that connect the top die to the package substrate through the at least one interposer.

公开(公告)号：US20250038163A1

公开(公告)日：2025-01-30

申请号：US18917500

申请日：2024-10-16

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Kemal AYGÜN ,  Suresh V. POTHUKUCHI ,  Xiaoqian LI ,  Omkar KARHADE

IPC: H01L25/18 ,  G02B6/42 ,  H01L23/373 ,  H01L23/538 ,  H01L25/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20240021522A1

公开(公告)日：2024-01-18

申请号：US18253945

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Tolga ACIKALIN ,  Tae Young YANG ,  Debabani CHOUDHURY ,  Shuhei YAMADA ,  Roya DOOSTNEJAD ,  Hosein NIKOPOUR ,  Issy KIPNIS ,  Oner ORHAN ,  Mehnaz RAHMAN ,  Kenneth P. FOUST ,  Christopher D. HULL ,  Telesphor KAMGAING ,  Omkar KARHADE ,  Stefano PELLERANO ,  Peter SAGAZIO ,  Sai VADLAMANI

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498 ,  H01Q1/22

CPC classification number: H01L23/5381 ,  H01L25/0652 ,  H01L24/16 ,  H01L23/66 ,  H01L23/49822 ,  H01Q1/2283 ,  H01L24/81 ,  H01L2924/14222 ,  H01L2924/1431 ,  H01L2223/6677 ,  H01L2223/6616 ,  H01L2223/6655 ,  H01L2224/16235 ,  H01L2224/16146

Abstract: Various devices, systems, and/or methods perform wireless chip to chip high speed data transmission. Strategies for such transmission include use of improved microbump antennas, wireless chip to chip interconnects, precoding and decoding strategies, channel design to achieve spatial multiplexing gain in line of sight transmissions, open cavity chip design for improved transmission, and/or mixed signal channel equalization.

公开(公告)号：US20230197520A1

公开(公告)日：2023-06-22

申请号：US17557579

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yi SHI ,  Omkar KARHADE ,  Shawna M. LIFF ,  Zhihua ZOU ,  Ryan MACKIEWICZ ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Arnab SARKAR

IPC: H01L21/822 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/822 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/15311

Abstract: Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.

公开(公告)号：US20230137877A1

公开(公告)日：2023-05-04

申请号：US17517152

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Omkar KARHADE ,  Malavarayan SANKARASUBRAMANIAN ,  Dingying XU ,  Gang DUAN ,  Bai NIE ,  Xiaoying GUO ,  Kristof DARMAWIKARTA ,  Hongxia FENG ,  Srinivas PIETAMBARAM ,  Jeremy D. ECTON

IPC: H01L23/00 ,  H01L25/065

Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

公开(公告)号：US20230101340A1

公开(公告)日：2023-03-30

申请号：US17485295

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kaveh HOSSEINI ,  Omkar KARHADE ,  Ravindranath V. MAHAJAN ,  Sergey Yuryevich SHUMARAYEV ,  Yew F. KOK ,  Sai VADLAMANI

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling an electronic package. In an embodiment, an electronic package comprises a package substrate with a stepped top surface, and a first die on a first plateau of the stepped top surface. In an embodiment, a second die is on a second plateau of the stepped top surface, where the second die extends over the first die, In an embodiment, a third die is on a third plateau of the stepped top surface, where the third die extends over the second die.

公开(公告)号：US20220413236A1

公开(公告)日：2022-12-29

申请号：US17358502

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Sushrutha Reddy GUJJULA ,  Tolga ACIKALIN ,  Ravindranath V. MAHAJAN ,  James E. JAUSSI ,  Chia-Pin CHIU

IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01S3/04

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to thermally and/or electrically coupling a thermal die to the surface of a photonic integrated circuit (PIC) within an open cavity in a substrate, where the thermal die is proximate to a laser on the PIC. Other embodiments may be described and/or claimed.

公开(公告)号：US20220196931A1

公开(公告)日：2022-06-23

申请号：US17131597

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Xiaoqian LI ,  Nitin DESHPANDE ,  Omkar KARHADE

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for coupling a micro-lens array to a photonics die. In embodiments, this coupling may be performed as an attach at a wafer level. In embodiments, wafer level optical testing of the photonics die with the attached micro-lens array may be tested electrically and optically before the photonics die is assembled into a package, in various configurations. Other embodiments may be described and/or claimed.

公开(公告)号：US20210405311A1

公开(公告)日：2021-12-30

申请号：US16911764

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Xiaoqian LI ,  Nitin DESHPANDE ,  Omkar KARHADE

IPC: G02B6/42 ,  G02B6/43

Abstract: Embodiments disclosed herein include electronic packages with photonics modules. In an embodiment, a photonics module comprises a carrier substrate and a photonics die over the carrier substrate. In an embodiment, the photonics die has a first surface facing away from the carrier substrate and a second surface facing the carrier substrate, and a plurality of V-grooves are disposed on the first surface proximate to an edge of the photonics die. In an embodiment, the photonics module further comprises a fiber connector attached to the photonics die, where the fiber connector couples a plurality of optical fibers to the photonics die. In an embodiment, individual ones of the plurality of optical fibers are positioned in the V-grooves.

公开(公告)号：US20200076046A1

公开(公告)日：2020-03-05

申请号：US16122609

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  William J. LAMBERT ,  Xiaoqian LI ,  Sidharth DALMIA

IPC: H01Q1/02 ,  H01Q1/22 ,  H03F3/24 ,  H03F3/195

Abstract: Embodiments include an electronic package that includes a radio frequency (RF) front end. In an embodiment, the RF front end may comprise a package substrate and a first die attached to a first surface of the package substrate. In an embodiment, the first die may include CMOS components. In an embodiment, the RF front end may further comprise a second die attached to the first surface of the package substrate. In an embodiment, the second die may comprise amplification circuitry. In an embodiment, the RF front end may further comprise an antenna attached to a second surface of the package substrate. In an embodiment, the second surface is opposite from the first surface.