公开(公告)号：US20190189236A1

公开(公告)日：2019-06-20

申请号：US16281559

申请日：2019-02-21

Applicant: Intel Corporation

Inventor： Pavel Poliakov ,  Andrey Kudryavtsev ,  Shekoufeh Qawami ,  Amirali Khatib Zadeh ,  Monte Klinkenborg

IPC: G11C29/38 ,  G06N3/04 ,  G06N3/08 ,  G11C29/44

CPC classification number: G11C29/38 ,  G06N3/04 ,  G06N3/08 ,  G11C29/44

Abstract: In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.

公开(公告)号：US10241710B2

公开(公告)日：2019-03-26

申请号：US15640373

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Shekoufeh Qawami ,  Raymond S. Tetrick ,  Frank T. Hady

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/10 ,  G11C16/00 ,  G11C7/10 ,  G06F12/08 ,  G06F12/1009 ,  G11C11/56

Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

公开(公告)号：US20190050049A1

公开(公告)日：2019-02-14

申请号：US16146454

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Nageen Himayat ,  Chaitanya Sreerama ,  Hassnaa Moustafa ,  Rita Wouhaybi ,  Linda Hurd ,  Nadine L Dabby ,  Van Le ,  Gayathri Jeganmohan ,  Ankitha Chandran

IPC: G06F1/32 ,  G06N5/04 ,  G06N99/00 ,  G06K9/00 ,  G06T15/00

Abstract: Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence are disclosed. An example computing device includes a hardware platform. The example computing device also includes an artificial intelligence (AI) engine to: determine a context of the device; and adjust an operation of the hardware platform based on an expected change in the context of the device. The adjustment modifies at least one of a computational efficiency of the device, a power efficiency of the device, or a memory response time of the device.

公开(公告)号：US10025737B2

公开(公告)日：2018-07-17

申请号：US14731183

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

IPC: G06F13/28 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G06F1/12 ,  G06F13/40 ,  G06F13/38 ,  H04L5/00 ,  H04L7/00

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

公开(公告)号：US20180088834A1

公开(公告)日：2018-03-29

申请号：US15281006

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1657 ,  G11C13/0004

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

公开(公告)号：US20170288885A1

公开(公告)日：2017-10-05

申请号：US15086207

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Amirali Khatib Zadeh ,  Shekoufeh Qawami ,  Abhranil Maiti

IPC: H04L9/32 ,  G06F12/02 ,  G06F12/14

CPC classification number: H04L9/3278 ,  G06F12/0246 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/7201 ,  G09C1/00

Abstract: In one embodiment, an apparatus comprises: a challenger logic to issue a challenge to a responder logic, the challenge including an address of a portion of an array of a non-volatile memory; and the responder logic to receive the challenge and read data from the portion of the array at a read time less than a lockout period and at a demarcation voltage. The challenger logic may be configured to verify the challenge if the read data matches an expected read value, where the expected read value is determined based on configuration parameter information including compensation data associated with the portion of the array. Other embodiments are described and claimed.

公开(公告)号：US09721657B1

公开(公告)日：2017-08-01

申请号：US15089507

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  Prashant S. Damle ,  Doyle Rivers ,  Julie M. Walker

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.

公开(公告)号：US20170075616A1

公开(公告)日：2017-03-16

申请号：US15214005

申请日：2016-07-19

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Shekoufeh Qawami ,  Raymond S. Tetrick ,  Frank T. Hady

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Abstract translation: 描述具有直接访问的多级存储器的示例。 示例包括指定用作计算机系统的存储器的非易失性随机存取存储器（NVRAM）的量。 示例还包括指定第二数量的NVRAM以用作计算设备的存储。 示例还包括重新指定第一数量的NVRAM的至少第一部分作为用作存储器的存储器。

公开(公告)号：US09430151B2

公开(公告)日：2016-08-30

申请号：US14879004

申请日：2015-10-08

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Shekoufeh Qawami ,  Raymond S. Tetrick ,  Frank T. Hady

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/10 ,  G11C16/00 ,  G11C7/10 ,  G06F12/08 ,  G11C11/56

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Abstract translation: 描述具有直接访问的多级存储器的示例。 示例包括指定用作计算机系统的存储器的非易失性随机存取存储器（NVRAM）的量。 示例还包括指定第二数量的NVRAM以用作计算设备的存储。 示例还包括重新指定第一数量的NVRAM的至少第一部分作为用作存储器的存储器。

公开(公告)号：US11762451B2

公开(公告)日：2023-09-19

申请号：US16147663

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Hassnaa Moustafa ,  Rita H. Wouhaybi ,  Nadine L. Dabby ,  Chaitanya Sreerama ,  Shekoufeh Qawami

IPC: G06F15/00 ,  G06F3/01 ,  G06N5/00 ,  G06N20/00 ,  G06F18/21 ,  G06F18/40 ,  G06F18/214 ,  G06V10/94 ,  G10L15/22 ,  G05B13/04 ,  G06V20/40

CPC classification number: G06F3/011 ,  G06F3/017 ,  G06F18/2148 ,  G06F18/2178 ,  G06F18/40 ,  G06N5/00 ,  G06N20/00 ,  G06V10/945 ,  G05B13/04 ,  G05B2219/42114 ,  G06V20/41 ,  G10L15/22 ,  G10L2015/223

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to add common sense to a human machine interface. Disclosed examples include a human machine interface system that having an actuator to cause artificial intelligence to execute in a virtual execution environment to generate a virtual response to a user input. The system also includes a virtual consequence evaluator to evaluate a virtual consequence that follows from the virtual response, the virtual consequence generated by executing a model of human interactions, and an output device controller to cause an output device to perform a non-virtual response to the user input when the virtual consequence evaluator evaluates the virtual consequence as positive.