公开(公告)号：US20160149129A1

公开(公告)日：2016-05-26

申请号：US14553632

申请日：2014-11-25

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The metal layer of the selector element can include conductive materials such as metal silicides, and metal silicon nitrides. Conductive materials of the MSM may include tantalum silicide, tantalum silicon nitride, titanium silicide, titanium silicon nitride, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择元件的金属层可以包括诸如金属硅化物的导电材料和金属硅氮化物。 MSM的导电材料可以包括硅化钽，氮化钽，硅化钛，氮化钛或其组合。

公开(公告)号：US20160148976A1

公开(公告)日：2016-05-26

申请号：US14554388

申请日：2014-11-26

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/145 ,  H01L45/149

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on a silicon semiconductor layer doped with both carbon and nitrogen. The metal layer of the selector element can include conductive materials such as carbon, tungsten, titanium nitride, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于掺杂有碳和氮的硅半导体层。 选择元件的金属层可以包括诸如碳，钨，氮化钛或其组合的导电材料。

公开(公告)号：US09246092B1

公开(公告)日：2016-01-26

申请号：US14554458

申请日：2014-11-26

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/148 ,  H01L29/768 ,  H01L45/00

CPC classification number: H01L45/00 ,  H01L27/2409 ,  H01L27/2418 ,  H01L45/08 ,  H01L45/1233

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can include insulator layers between the semiconductor layer and the metal layers to lower the leakage current of the device. The metal layers of the selector element can include conductive materials such as tungsten, titanium nitride, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以包括半导体层和金属层之间的绝缘体层，以降低器件的漏电流。 选择元件的金属层可以包括诸如钨，氮化钛或其组合的导电材料。

公开(公告)号：US20150236260A1

公开(公告)日：2015-08-20

申请号：US14702374

申请日：2015-05-01

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E. Lazovsky

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract translation: 本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极 第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。 第二电极设置在嵌入式电阻式存储单元内靠近第一电极。 第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。 第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

公开(公告)号：US20150184286A1

公开(公告)日：2015-07-02

申请号：US14145337

申请日：2013-12-31

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Andrew Steinbach

IPC: C23C16/24 ,  C23C14/14 ,  C23C14/34 ,  C23C14/48 ,  C23C16/56

CPC classification number: C23C16/24 ,  C23C14/14 ,  C23C14/5806 ,  C23C14/5826 ,  C23C14/5846 ,  C23C16/56 ,  H01J37/32357 ,  H01J37/32917 ,  H01J37/32935 ,  H01J37/3405

Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

Abstract translation: 非晶硅（a-Si）被氢化用作超导电子器件的电介质（例如，层间电介质）。 通过CVD或溅射在衬底上形成氢化a-Si层。 在a-Si沉积期间或之后，氢可以被整合。 在形成层之后，首先在高氢化学势的环境中退火，随后在低氢化学势的环境中退火。 任选地，在从低氢化学势的环境中除去衬底之前，可以用氢气阻挡层将a-Si（或者如果加入的是H-可渗透的覆盖层）封盖。

公开(公告)号：US08995166B2

公开(公告)日：2015-03-31

申请号：US13721279

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Dipankar Pramanik ,  David E Lazovsky ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C11/56 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/145 ,  H01L45/1608

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract translation: 提供了用于多位数据存储的电阻器阵列，而不需要增加存储器芯片的尺寸或缩小存储器芯片中包含的存储器单元的特征尺寸。 电阻器阵列包括多个离散电阻元件，以便以不同的串联组合方式连接到至少一个存储器单元或存储器件。 在一种配置中，通过将每个存储器单元或设备连接至少一个电阻器阵列，在连接的存储器件的电阻式开关存储器元件中发现的电阻式开关层能够处于多个电阻状态，用于存储多位数字信息。 在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，连接的存储器件中的电阻式开关层可以处于期望的电阻状态。

公开(公告)号：US08975114B2

公开(公告)日：2015-03-10

申请号：US13804318

申请日：2013-03-14

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L21/00 ,  H01L21/16 ,  H01L45/00 ,  H01L27/10 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的存储器件和方法。 在一个实施例中，一种用于制造电阻式开关存储器件的方法包括在设置在衬底上的下电极上沉积金属层，并将该金属层暴露于活性氧源，同时将衬底加热到​​约300的范围内的氧化温度 约600℃，并且在氧化过程中从金属层的上部形成金属氧化物层。 下部电极含有硅材料，金属层含有铪或锆。 在氧化处理之后，该方法还包括将衬底加热至大于600℃至约850℃的范围内的退火温度，同时在硅化期间从金属层的下部形成金属硅化物层 处理。

公开(公告)号：US20150064873A1

公开(公告)日：2015-03-05

申请号：US14527276

申请日：2014-10-29

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

公开(公告)号：US20150056749A1

公开(公告)日：2015-02-26

申请号：US14506298

申请日：2014-10-03

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

Abstract translation: 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

公开(公告)号：US08859093B2

公开(公告)日：2014-10-14

申请号：US13728889

申请日：2012-12-27

Applicant: Intermolecular, Inc.

Inventor： Xuena Zhang ,  Dipankar Pramanik

IPC: C03C17/09 ,  C03C17/30 ,  C03C17/38 ,  C03C17/00 ,  C03C17/36

CPC classification number: C03C17/36 ,  C03C17/3636 ,  C03C17/3644 ,  Y10T428/261 ,  Y10T428/265 ,  Y10T428/31612 ,  Y10T428/31678

Abstract: Embodiments of the present invention include low emissivity (low-E) coatings and methods for forming the coatings. The low-E coating comprises a self-assembled monolayer (SAM) on a glass substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the glass substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the low-E coating comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n−2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as silver. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic. The coating can further comprise an antireflection coating on the metal layer.

Abstract translation: 本发明的实施例包括低发射率（低E）涂层和形成涂层的方法。 低E涂层包括在玻璃基板上的自组装单层（SAM），其中SAM的一个表面设置成与玻璃基板接触并共价结合到玻璃基板上，单层的一个表面设置成与 共价键合到金属层。 在一些实施方案中，低E涂层包含以下结构的一个或多个单体亚单位的组合：Si-（CnHy） - （LM）m，其中n为1至20，y为2n-2至2n， m为1〜3，L为VI族元素，M为银等金属。 在一些实施方案中，（C n H y）可以是支链，交联或环状的。 涂层还可以包括在金属层上的抗反射涂层。