公开(公告)号：US20140073107A1

公开(公告)日：2014-03-13

申请号：US13897050

申请日：2013-05-17

Applicant: Intermolecular Inc.

Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

Abstract translation: 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

公开(公告)号：US20130214808A1

公开(公告)日：2013-08-22

申请号：US13849749

申请日：2013-03-25

Applicant: Intermolecular, Inc.

Inventor： Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

IPC: G01R31/26

CPC classification number: G01R31/26 ,  G01N21/55 ,  G01R31/2607 ,  H02S50/10

Abstract: Measuring current-voltage (I-V) characteristics of a solar cell using a lamp that emits light, a substrate that includes a plurality of solar cells, a positive electrode attached to the solar cells, and a negative electrode peripherally deposited around each of the solar cells and connected to a common ground, an articulation platform coupled to the substrate, a multi-probe switching matrix or a Z-stage device, a programmable switch box coupled to the multi-probe switching matrix or Z-stage device and selectively articulating the probes by raising the probes until in contact with at least one of the positive electrode and the negative electrode and lowering the probes until contact is lost with at least one of the positive electrode and the negative electrode, a source meter coupled to the programmable switch box and measuring the I-V characteristics of the substrate.

Abstract translation: 使用发光灯的太阳能电池测量电流 - 电压（IV）特性，包括多个太阳能电池的基板，附着到太阳能电池的正电极和周围沉积在每个太阳能电池周围的负电极 并且连接到公共接地，耦合到衬底的关节式平台，多探针开关矩阵或Z级装置，耦合到多探针开关矩阵或Z级装置的可编程开关盒，并且选择性地将探针 通过将探针升高直到与正电极和负电极中的至少一个接触并且降低探针，直到与正电极和负电极中的至少一个接触而丢失，源计量器耦合到可编程开关盒和 测量衬底的IV特性。

公开(公告)号：US09246085B1

公开(公告)日：2016-01-26

申请号：US14338949

申请日：2014-07-23

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/08 ,  H01L27/24 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/165 ,  H01L45/1658

Abstract: Filament size and shape in a ReRAM stack can be controlled by doping layers of a variable-resistance stack to change the crystallization temperature. This changes the density of the grain boundaries that form during annealing and provide minimal-resistance paths for the migration of charged defects. Hf, Zr, or Ti decreases the crystallization temperature and narrows the filament, while Si or N increases the crystallization temperature and widens the filament. Tapered filaments are of interest: The narrow tip requires little energy to break and re-form, enabling the cell to operate at low power, yet the wider body and base are insensitive to entropic behavior of small numbers of defects, enabling the cell to retain data for long periods.

Abstract translation: 可以通过掺杂可变电阻堆叠层来控制ReRAM堆叠中的长丝尺寸和形状来改变结晶温度。 这改变了在退火期间形成的晶界的密度，并且为带电缺陷的迁移提供了最小的电阻路径。 Hf，Zr或Ti会降低结晶温度并使丝变窄，而Si或N则会增加结晶温度并加长丝。 锥形丝是令人感兴趣的：窄尖端需要很少的能量来破坏和重新形成，使得细胞能够以低功率运行，但是更宽的身体和基部对少数缺陷的熵行为不敏感，使细胞保留 长时间的数据。

公开(公告)号：US09245649B2

公开(公告)日：2016-01-26

申请号：US14108877

申请日：2013-12-17

Applicant: Intermolecular Inc.

Inventor： Federico Nardi ,  Ryan C. Clarke ,  Yun Wang

IPC: G11C27/02 ,  G11C13/00

CPC classification number: G11C27/02 ,  G11C13/0002 ,  G11C13/0007

Abstract: A nonvolatile sample and hold circuit can include a resistive switching circuit, a sample circuit, a reset circuit, and a converter circuit. The resistive switching circuit can be operable to accept an input voltage Vg, and provide a resistance response Rrs that corresponds to the input signal Vg. The sampling circuit can be operable to sample an input signal such as an input voltage Vin, to provide a sampled voltage Vg. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The converter circuit can be operable to convert the resistive switching circuit to an output voltage. The novel sample and hold circuit can have no issues related to charge injection, no settling time and instantaneous sampling time, together with potentially infinite hold time.

Abstract translation: 非易失性采样和保持电路可以包括电阻开关电路，采样电路，复位电路和转换器电路。 电阻开关电路可操作以接受输入电压Vg，并且提供对应于输入信号Vg的电阻响应Rrs。 采样电路可以用于对诸如输入电压Vin的输入信号进行采样，以提供采样电压Vg。 复位电路可以用于将电阻式开关电路复位到高电阻状态。 转换器电路可操作以将电阻开关电路转换成输出电压。 新颖的采样和保持电路可以没有与电荷注入相关的问题，无需建立时间和瞬间采样时间，以及潜在的无限延时时间。

公开(公告)号：US20160020388A1

公开(公告)日：2016-01-21

申请号：US14336830

申请日：2014-07-21

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1625

Abstract: A variable resistance layer in a resistive non-volatile memory (ReRAM) cell changes its resistance in response to an applied signal by breaking and re-forming covalent bonds (e.g., in sub-stoichiometric silicon oxide). Resistivity decreases with increasing density of broken “dangling” bonds. When an electric field is applied, more dangling bonds are created, forming a filament of defects through which charge carriers can tunnel through the covalent layer. Passing a high current through the dangling-bond filament causes localized heating that re-forms the bonds. Optionally, an ionic oxide or nitride layer in contact with the covalent switching layer may serve as an oxygen source for thermal re-oxidation during the heating.

Abstract translation: 电阻式非易失性存储器（ReRAM）单元中的可变电阻层通过破坏和重新形成共价键（例如，在亚化学计量的氧化硅中）而响应于所施加的信号改变其电阻。 电阻率随断裂“悬挂”键密度的增加而降低。 当施加电场时，产生更多的悬挂键，形成电荷载流子穿过共价层的缺陷细丝。 将高电流通过悬挂键丝引起局部加热，重新形成粘结。 任选地，与共价开关层接触的离子氧化物或氮化物层可以用作加热期间的热再氧化的氧源。

公开(公告)号：US09184379B1

公开(公告)日：2015-11-10

申请号：US14335504

申请日：2014-07-18

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang

IPC: H01L45/00 ,  H01L21/00 ,  H01L49/02 ,  H01L21/70 ,  H01L23/522 ,  H01L27/01 ,  H01L27/24

CPC classification number: H01L21/00 ,  H01L21/707 ,  H01L23/5228 ,  H01L27/016 ,  H01L27/249 ,  H01L28/20 ,  H01L28/24 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin cap of metal alloy or metal-silicon compound is formed over a ternary oxide or ternary nitride ReRAM embedded resistor. At least one metal in the cap is the same as a metal in the embedded resistor. If the cap oxidizes slightly (e.g., incidental to a vacuum break, anneal, or subsequent treatment or deposition), the overall resistance of the memory cell is much less affected than it would be by the same amount of oxidation directly on a surface of the uncapped oxide or nitride embedded resistor.

Abstract translation: 在三元氧化物或三元氮化物ReRAM嵌入式电阻器上形成金属合金或金属 - 硅化合物的薄盖。 帽中的至少一个金属与嵌入式电阻器中的金属相同。 如果盖稍微氧化（例如偶然发生真空破坏，退火或随后的处理或沉积），则记忆单元的整体电阻比直接在其表面上的相同量的氧化物受到的影响要小得多 未封装的氧化物或氮化物嵌入式电阻器。

公开(公告)号：US09105563B2

公开(公告)日：2015-08-11

申请号：US13713421

申请日：2012-12-13

Applicant: Intermolecular, Inc.

Inventor： Charlene Chen ,  Tony P. Chiang ,  Chi-I Lang ,  Yun Wang

IPC: G01N21/59 ,  H01L21/66 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L22/20 ,  G01N21/59 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/0262 ,  H01L22/12 ,  H01L29/1606

Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second results.

Abstract translation: 一种方法和系统包括第一衬底和第二衬底，每个衬底在光的预定波长处包括预定的基线透射率值，第一衬底上的处理区域通过组合地改变材料，工艺条件，单元工艺中的至少一个和 与所述石墨烯生产相关联的工艺序列，对所述第一衬底上的所述经处理区域执行第一表征测试以产生第一结果，通过改变材料，工艺条件，单位过程中的至少一种以组合方式处理第二衬底上的区域， 以及基于第一表征测试的第一结果与石墨烯生产相关联的处理顺序，对第二衬底上的经处理区域执行第二表征测试以产生第二结果，以及确定第一衬底和第二衬底中的至少一个 基板满足预定的质量阈值 基于第二个结果。

公开(公告)号：US20150200361A1

公开(公告)日：2015-07-16

申请号：US14618055

申请日：2015-02-10

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Hieu Pham ,  Vidyut Gopal ,  Imran Hashim ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi ,  Hong Sheng Yang

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract translation: 本发明的实施例包括非易失性存储器元件和包括非易失性存储元件的存储器件。 还公开了形成非易失性存储元件的方法。 非易失性存储元件包括第一电极层，第二电极层和设置在第一和第二电极层之间的多个氧化物层。 氧化物层中的一个具有线性电阻和亚化学计量组成，另一个氧化物层具有双稳态电阻和近化学计量组成。 优选地，两个氧化物层厚度的总和在约和之间，并且具有双稳态电阻的氧化物层具有在总厚度的约25％至约75％之间的厚度。 在一个实施例中，氧化物层在具有受控的氩气和氧气的气氛中使用反应溅射形成。

公开(公告)号：US20150187841A1

公开(公告)日：2015-07-02

申请号：US14140723

申请日：2013-12-26

Applicant: Intermolecular Inc.

Inventor： Yun Wang ,  Mihir Tendulkar ,  Milind Weling

IPC: H01L27/24 ,  H01L49/02 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2481 ,  H01L28/24 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a variable resistance layer that are interconnected in series by, for example, stacking the two. The embedded resistor prevents excessive electrical currents through the variable resistance layer thereby preventing its over-programming. The embedded resistor is configured to maintain a constant resistance during the operation of the ReRAM cell, such as applying switching currents and changing the resistance of the variable resistance layer. Specifically, the embedded resistor may be electrically broken down during fabrication of the ReRAM cell to improve the subsequent stability of the embedded resistance to electrical fields during operation of the ReRAM cell. The embedded resistor may be made from materials that allow this initial breakdown and to avoid future breakdowns, such metal silicon nitrides, metal aluminum nitrides, and metal boron nitrides.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 ReRAM单元包括嵌入式电阻器和可变电阻层，其通过例如堆叠两者串联互连。 嵌入式电阻器阻止通过可变电阻层的过大电流，从而防止其过度编程。 嵌入式电阻器被配置为在ReRAM单元的操作期间保持恒定的电阻，例如施加开关电流并改变可变电阻层的电阻。 具体地说，在ReRAM单元的制造期间，嵌入式电阻器可能被电分解，以提高在ReRAM单元操作期间嵌入电阻对电场的后续稳定性。 嵌入式电阻器可以由允许该初始击穿并避免将来击穿的材料制成，例如金属氮化硅，金属氮化铝和金属氮化硼。

公开(公告)号：US20150170760A1

公开(公告)日：2015-06-18

申请号：US14108877

申请日：2013-12-17

Applicant: Intermolecular Inc.

Inventor： Federico Nardi ,  Ryan C. Clarke ,  Yun Wang

IPC: G11C27/02

CPC classification number: G11C27/02 ,  G11C13/0002 ,  G11C13/0007

Abstract: A nonvolatile sample and hold circuit can include a resistive switching circuit, a sample circuit, a reset circuit, and a converter circuit. The resistive switching circuit can be operable to accept an input voltage Vg, and provide a resistance response Rrs that corresponds to the input signal Vg. The sampling circuit can be operable to sample an input signal such as an input voltage Vin, to provide a sampled voltage Vg. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The converter circuit can be operable to convert the resistive switching circuit to an output voltage. The novel sample and hold circuit can have no issues related to charge injection, no settling time and instantaneous sampling time, together with potentially infinite hold time.

Abstract translation: 非易失性采样和保持电路可以包括电阻开关电路，采样电路，复位电路和转换器电路。 电阻开关电路可操作以接受输入电压Vg，并且提供对应于输入信号Vg的电阻响应Rrs。 采样电路可以用于对诸如输入电压Vin的输入信号进行采样，以提供采样电压Vg。 复位电路可以用于将电阻式开关电路复位到高电阻状态。 转换器电路可操作以将电阻开关电路转换成输出电压。 新颖的采样和保持电路可以没有与电荷注入相关的问题，无需建立时间和瞬间采样时间，以及潜在的无限延时时间。