公开(公告)号：US10141426B2

公开(公告)日：2018-11-27

申请号：US15017868

申请日：2016-02-08

申请人： International Business Machines Corporation

发明人： Brent A. Anderson ,  Huiming Bu ,  Fee Li Lie ,  Shogo Mochizuki ,  Junli Wang

IPC分类号： H01L29/66 ,  H01L21/306 ,  H01L21/324 ,  H01L21/308 ,  H01L29/417 ,  H01L29/78 ,  H01L21/225 ,  H01L21/3065 ,  H01L29/423 ,  H01L29/786

摘要： According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.

公开(公告)号：US20170323794A1

公开(公告)日：2017-11-09

申请号：US15654882

申请日：2017-07-20

申请人： International Business Machines Corporation

发明人： Brent A. Anderson ,  Huiming Bu ,  Terence B. Hook ,  Fee Li Lie ,  Junli Wang

IPC分类号： H01L21/285 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L23/535

CPC分类号： H01L21/28518 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

摘要： A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.

公开(公告)号：US20170317210A1

公开(公告)日：2017-11-02

申请号：US15139937

申请日：2016-04-27

申请人： International Business Machines Corporation

发明人： Brent A. Anderson ,  Huiming Bu ,  Fee Li Lie ,  Edward J. Nowak ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/66666

摘要： Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.

公开(公告)号：US20170287776A1

公开(公告)日：2017-10-05

申请号：US15625360

申请日：2017-06-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02

CPC分类号： H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US20170229556A1

公开(公告)日：2017-08-10

申请号：US15284563

申请日：2016-10-04

申请人： International Business Machines Corporation

发明人： Brent A. Anderson ,  Huiming Bu ,  Fee Li Lie ,  Shogo Mochizuki ,  Junli Wang

IPC分类号： H01L29/66 ,  H01L21/324 ,  H01L29/786 ,  H01L21/308 ,  H01L29/423 ,  H01L21/225 ,  H01L21/3065

CPC分类号： H01L29/66795 ,  H01L21/22 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/324 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.

公开(公告)号：US20170076987A1

公开(公告)日：2017-03-16

申请号：US15342801

申请日：2016-11-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

摘要翻译： 用于填充结构之间的间隙的方法包括通过间隙形成彼此相邻的多个高纵横比结构，在结构的顶部上形成第一介电层，并在结构上共形沉积间隔电介质层。 间隔电介质层从水平表面去除，保护层共形沉积在结构上。 间隙填充有可流动电介质，其通过选择性蚀刻工艺凹陷到结构侧壁的高度，使得保护层保护结构侧壁上的间隔电介质层。 使用比保护层更高的蚀刻电阻将第一介电层和间隔电介质层暴露在高度之上，以通过蚀刻工艺保持间隔层电介质的尺寸。 间隙由高密度等离子体填充物填充。

公开(公告)号：US09583563B1

公开(公告)日：2017-02-28

申请号：US14922939

申请日：2015-10-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Huiming Bu ,  Sivananda K. Kanakasabapathy ,  Fee Li Lie ,  Tenko Yamashita

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/1083 ,  H01L21/223 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66803

摘要： A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.

摘要翻译： 一种形成穿孔停止区域的方法，该方法包括在相邻翅片结构之间形成第一电介质材料的隔离区域，并且在翅片结构的侧壁上形成第二电介质材料的间隔物。 隔离区域的第一介电材料可以用对第二电介质材料有选择性以暴露鳍结构的基底侧壁部分的蚀刻工艺来凹陷。 气相掺杂可以将第一导电类型的掺杂剂引入翅片结构的基底侧壁部分，形成鳍片结构的沟道区域下方的穿通停止区域。

公开(公告)号：US09548379B1

公开(公告)日：2017-01-17

申请号：US14949964

申请日：2015-11-24

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Sivananda K. Kanakasabapathy ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/324 ,  H01L21/265 ,  H01L21/02 ,  H01L21/225

CPC分类号： H01L29/66803 ,  H01L21/0257 ,  H01L21/02636 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7835 ,  H01L29/785 ,  H01L2029/7858

摘要： An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the semiconductor substrate to define a fin length. A plurality of gate structures wrap around the sidewalls and upper fin surface of the fin. The plurality of gate structures includes at least one desired gate structure surrounded by at least one sacrificial gate structure. A first source/drain region is formed adjacent a first sidewall of the at least one desired gate structure, and a second source/drain region is formed adjacent a second sidewall of the at least one desired gate structure opposite the first sidewall. The dimensions of the first and second source/drain regions are asymmetrical with respect to one another.

摘要翻译： 非对称finFET器件包括在半导体衬底的上表面上的至少一个半导体鳍片。 鳍沿着半导体衬底的长度延伸以限定翅片长度。 多个栅极结构围绕鳍的侧壁和上鳍表面缠绕。 多个栅极结构包括由至少一个牺牲栅极结构包围的至少一个期望的栅极结构。 在所述至少一个期望的栅极结构的第一侧壁附近形成第一源极/漏极区域，并且与所述至少一个期望的栅极结构的与第一侧壁相对的第二侧壁附近形成第二源极/漏极区域。 第一和第二源极/漏极区域的尺寸相对于彼此不对称。

公开(公告)号：US09543435B1

公开(公告)日：2017-01-10

申请号：US14887384

申请日：2015-10-20

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Sivananda K. Kanakasabapathy ,  Tenko Yamashita

IPC分类号： H01L29/735 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC分类号： H01L29/66803 ,  H01L21/0257 ,  H01L21/02636 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7835 ,  H01L29/785 ,  H01L2029/7858

摘要： An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the semiconductor substrate to define a fin length. A plurality of gate structures wrap around the sidewalls and upper fin surface of the fin. The plurality of gate structures includes at least one desired gate structure surrounded by at least one sacrificial gate structure. A first source/drain region is formed adjacent a first sidewall of the at least one desired gate structure, and a second source/drain region is formed adjacent a second sidewall of the at least one desired gate structure opposite the first sidewall. The dimensions of the first and second source/drain regions are asymmetrical with respect to one another.

摘要翻译： 非对称finFET器件包括在半导体衬底的上表面上的至少一个半导体鳍片。 鳍沿着半导体衬底的长度延伸以限定翅片长度。 多个栅极结构围绕鳍的侧壁和上鳍表面缠绕。 多个栅极结构包括由至少一个牺牲栅极结构包围的至少一个期望的栅极结构。 在所述至少一个期望的栅极结构的第一侧壁附近形成第一源极/漏极区域，并且与所述至少一个期望的栅极结构的与第一侧壁相对的第二侧壁附近形成第二源极/漏极区域。 第一和第二源极/漏极区域的尺寸相对于彼此不对称。

公开(公告)号：US20160379873A1

公开(公告)日：2016-12-29

申请号：US14750741

申请日：2015-06-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

摘要翻译： 用于填充结构之间的间隙的方法包括通过间隙形成彼此相邻的多个高纵横比结构，在结构的顶部上形成第一介电层，并在结构上共形沉积间隔电介质层。 间隔电介质层从水平表面去除，保护层共形沉积在结构上。 间隙填充有可流动电介质，其通过选择性蚀刻工艺凹陷到结构侧壁的高度，使得保护层保护结构侧壁上的间隔电介质层。 使用比保护层更高的蚀刻电阻将第一介电层和间隔电介质层暴露在高度之上，以通过蚀刻工艺保持间隔层电介质的尺寸。 间隙由高密度等离子体填充物填充。