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38 条记录 (耗时 0.034 秒)

    Embedded waveguide detectors
    21.
    发明申请
    Embedded waveguide detectors 审中-公开
    嵌入式波导检测器

    公开(公告)号：US20070018270A1

    公开(公告)日：2007-01-25

    申请号：US11484009

    申请日：2006-07-10

    申请人： Francisco Leon ,  Lawrence West ,  Yuichi Wada ,  Gregory Wojcik ,  Stephen Moffatt

    发明人： Francisco Leon ,  Lawrence West ,  Yuichi Wada ,  Gregory Wojcik ,  Stephen Moffatt

    IPC分类号： H01L31/00

    CPC分类号： G02B6/12004 ,  G02B2006/12061 ,  H01L31/0232 ,  H01L31/0288 ,  H01L31/105 ,  H01L31/1812 ,  Y02E10/50

    摘要： A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.

    摘要翻译： 一种制造检测器的方法，包括：在衬底中形成沟槽，所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中，所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层，第二层和第三层的部分，以产生上部基本平坦的表面，并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。

    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
    25.
    发明授权
    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires 失效
    用于制造基于导电聚合物和半导体纳米线的塑料电子器件的完全集成的有机分层工艺

    公开(公告)号：US07345307B2

    公开(公告)日：2008-03-18

    申请号：US11233503

    申请日：2005-09-22

    申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    IPC分类号： H01L29/10

    CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

    摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

    摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

    Self-aligned implanted waveguide detector
    27.
    发明申请
    Self-aligned implanted waveguide detector 审中-公开

    公开(公告)号：US20070272996A1

    公开(公告)日：2007-11-29

    申请号：US11787187

    申请日：2007-04-13

    申请人： Francisco Leon ,  Lawrence West

    发明人： Francisco Leon ,  Lawrence West

    IPC分类号： H01L31/075 ,  H01L31/18

    CPC分类号： H01L31/035254 ,  B82Y20/00 ,  G02B6/12004

    摘要： A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.

    Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires
    29.
    发明申请
    Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires 审中-公开
    基于导电聚合物和半导体纳米线制造塑料电子的全集成有机分层工艺

    公开(公告)号：US20080128688A1

    公开(公告)日：2008-06-05

    申请号：US12016701

    申请日：2008-01-18

    申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    IPC分类号： H01L51/05

    CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

    摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

    摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

    Artificial dielectrics using nanostructures
    30.
    发明申请
    Artificial dielectrics using nanostructures 失效
    使用纳米结构的人造电介质

    公开(公告)号：US20070296032A1

    公开(公告)日：2007-12-27

    申请号：US11203432

    申请日：2005-08-15

    申请人： David Stumbo ,  Stephen Empedocles ,  Francisco Leon ,  J. Parce

    发明人： David Stumbo ,  Stephen Empedocles ,  Francisco Leon ,  J. Parce

    IPC分类号： H01L27/12

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  G11C2213/16 ,  G11C2213/81 ,  H01L29/0673 ,  H01L29/4908 ,  H01L51/0537 ,  Y10S977/743 ,  Y10S977/745 ,  Y10S977/762 ,  Y10S977/813 ,  Y10S977/936

    摘要： Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric constants can be achieved with an artificial dielectric using nanostructures. The dielectric constant can be adjusted by varying the length, diameter, carrier density, shape, aspect ratio, orientation and density of the nanostructures. Additionally, a controllable artificial dielectric using nanostructures, such as nanowires, is disclosed in which the dielectric constant can be dynamically adjusted by applying an electric field to the controllable artificial dielectric. A wide range of electronic devices can use artificial dielectrics with nanostructures to improve performance. Example devices include, capacitors, thin film transistors, other types of thin film electronic devices, microstrip devices, surface acoustic wave (SAW) filters, other types of filters, and radar attenuating materials

    摘要翻译： 公开了使用纳米结构的人造电介质，例如纳米线。 在实施例中，公开了使用其他纳米结构的人造电介质，例如纳米棒，纳米管或纳米带等。 人造电介质包括具有嵌入电介质材料内的多个纳米线（或其他纳米结构）的电介质材料。 使用纳米结构的人造电介质可以实现非常高的介电常数。 可以通过改变纳米结构的长度，直径，载流子密度，形状，纵横比，取向和密度来调节介电常数。 此外，公开了使用纳米结构的可控人造电介质，例如纳米线，其中可以通过向可控人造电介质施加电场来动态地调整介电常数。 各种电子器件可以使用具有纳米结构的人造电介质来提高性能。 示例性器件包括电容器，薄膜晶体管，其他类型的薄膜电子器件，微带器件，表面声波（SAW）滤波器，其它类型的滤波器以及雷达衰减材料