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28 条记录 (耗时 0.031 秒)

    Piezo-electric relay
    25.
    发明授权
    Piezo-electric relay 失效
    PIEZO电继电器

    公开(公告)号：US5093600A

    公开(公告)日：1992-03-03

    申请号：US098535

    申请日：1987-09-18

    申请人： James E. Kohl

    发明人： James E. Kohl

    IPC分类号： H01H57/00

    CPC分类号： H01H57/00

    摘要： A piezoelectric relay requiring less piezoelectric material than conventional piezoelectric relays is disclosed. The relay differs from conventional relays in that the contacts are touching with essentially no force applied between the contacts when no power is applied to the relay.

    摘要翻译： 公开了一种压电继电器，它比传统的压电继电器要求更少的压电材料。 继电器与常规继电器的不同之处在于，当没有电源施加到继电器时，触点基本上没有施加在触点之间的力而接触。

    Inverted groove isolation technique for merging dielectrically isolated semiconductor devices
    26.
    发明授权
    Inverted groove isolation technique for merging dielectrically isolated semiconductor devices 失效
    用于并联电介质隔离半导体器件的倒槽隔离技术

    公开(公告)号：US4982262A

    公开(公告)日：1991-01-01

    申请号：US691749

    申请日：1985-01-15

    申请人： Adrian R. Hartman ,  James E. Kohl ,  Robert S. Scott ,  Harry T. Weston

    发明人： Adrian R. Hartman ,  James E. Kohl ,  Robert S. Scott ,  Harry T. Weston

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/082

    CPC分类号： H01L21/76297

    摘要： An area saving dielectrically isolated semiconductor structure is disclosed which allows for the merger of a plurality of active devices, which share a common terminal, in a single dielectrically isolated (DI) island, or tub. In particular, an isolation groove is formed in the bottom of the DI tub and extends upwards toward the top surface of the semiconductor structure. The common diffusion region associated with the common terminal is located in the DI tub directly over the isolation groove. The isolation groove and common diffusion region thus separate the single DI tub into isolated sections, where a separate active device can be formed in each section. Isolation is achieved through the interaction of the groove with the common diffusion region to "pinch off" the conductive channel between devices in the DI tub. In a preferred embodiment, an inverted V-shaped isolation groove is utilized so as not to complicate the fabrication process. In order to merge a large plurality of devices in a single DI tub, a plurality of isolation grooves may be utilized to divide the single DI tub into a number of separate isolated sections.

    摘要翻译： 公开了一种省电介质绝缘半导体结构，其允许在单个介电隔离（DI）岛或桶中共享公共端子的多个有源器件的合并。 特别地，隔离槽形成在DI桶的底部并向上朝向半导体结构的顶表面延伸。 与公共端子相关联的公共扩散区域直接位于隔离槽的DI桶中。 隔离沟槽和公共扩散区域因此将单个DI桶分离成隔离的部分，其中可以在每个部分中形成单独的有源器件。 通过槽与公共扩散区的相互作用来实现隔离，以“夹紧”DI桶中的设备之间的导电通道。 在优选实施例中，使用倒V形隔离槽，以免使制造过程复杂化。 为了将大量多个装置合并在单个DI桶中，可以使用多个隔离槽将单个DI桶分成多个单独的隔离部分。

    High voltage semiconductor devices electrically isolated from an integrated circuit substrate
    27.
    发明授权
    High voltage semiconductor devices electrically isolated from an integrated circuit substrate 失效
    与集成电路基板电隔离的高电压半导体器件

    公开(公告)号：US4661838A

    公开(公告)日：1987-04-28

    申请号：US790716

    申请日：1985-10-24

    申请人： Eric J. Wildi ,  James E. Kohl

    发明人： Eric J. Wildi ,  James E. Kohl

    IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/40 ,  H01L29/80 ,  H01L29/90

    CPC分类号： H01L29/7391

    摘要： High voltage semiconductor devices include a drift layer region underlying a field gate electrode, the drift layer region having a selected charge density of lesser magnitude than the charge density of the remainder of the drift layer. This tailoring of the charge density of the drift layer region lowers the pinch-off voltage of a MOSFET inherent in the drift layer region. This lower pinch-off voltage decreases the potential of a device buried-layer when the device is in a reverse blocking mode of operation.

    摘要翻译： 高电压半导体器件包括场栅电极下面的漂移层区域，漂移层区域具有比漂移层的其余部分的电荷密度小的量级的选定电荷密度。 漂移层区域的电荷密度的这种调整降低了漂移层区域固有的MOSFET的夹断电压。 当器件处于反向阻塞工作模式时，此较低的夹断电压会降低器件掩埋层的电位。