公开(公告)号：US11783888B2

公开(公告)日：2023-10-10

申请号：US17472361

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Hiroshi Maejima

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  H10B43/10 ,  G11C7/18

CPC classification number: G11C11/4091 ,  G11C5/06 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C7/18 ,  H10B43/10

Abstract: According to one embodiment, a semiconductor memory device includes a first bit line extending in a first direction and coupled to a first memory cell, a first pad coupled to the first bit line, a first sense amplifier coupled to the first pad, a second bit line being adjacent to the first bit line and extending in the first direction and coupled to a second memory cell, a second pad coupled to the second bit line, and a second sense amplifier coupled to the second pad. The first and second sense amplifiers are adjacent to each other and are arranged in a second direction intersecting the first direction. The first and second pads are adjacent to each other and are arranged in a third direction intersecting the first direction and the second direction.

公开(公告)号：US20230307016A1

公开(公告)日：2023-09-28

申请号：US17807802

申请日：2022-06-20

Applicant: Kioxia Corporation

Inventor： Hiroshi Maejima ,  Toshifumi Hashimoto

IPC: G11C7/10 ,  G11C7/08 ,  G11C16/16

CPC classification number: G11C7/1039 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109 ,  G11C16/16

Abstract: A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.

公开(公告)号：US11568936B2

公开(公告)日：2023-01-31

申请号：US17502573

申请日：2021-10-15

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Maejima

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/28 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/32

Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

公开(公告)号：US11430521B2

公开(公告)日：2022-08-30

申请号：US16911461

申请日：2020-06-25

Applicant: Kioxia Corporation

Inventor： Hiroshi Maejima

IPC: G11C16/04 ,  G11C16/10 ,  G11C5/02 ,  G11C5/06 ,  G11C16/08 ,  G11C16/34

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

公开(公告)号：US11411016B2

公开(公告)日：2022-08-09

申请号：US17005535

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Hiroshi Maejima ,  Kenichiro Yoshii ,  Takashi Maeda ,  Hideo Wada

IPC: H01L27/11565 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11578 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11563 ,  H01L27/11568

Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.

公开(公告)号：US11049573B2

公开(公告)日：2021-06-29

申请号：US16802471

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Hidehiro Shiga ,  Hiroshi Maejima

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.

公开(公告)号：US11889699B2

公开(公告)日：2024-01-30

申请号：US18100615

申请日：2023-01-24

Applicant: Kioxia Corporation

Inventor： Naohito Morozumi ,  Hiroshi Maejima

IPC: H10B43/40 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  H01L23/00 ,  G11C7/06 ,  H10B43/10 ,  H10B43/35 ,  G11C5/02

CPC classification number: H10B43/40 ,  G11C5/025 ,  G11C7/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  H01L24/05 ,  H01L24/20 ,  H10B43/10 ,  H10B43/35 ,  H01L2924/1438

Abstract: A semiconductor memory device including a substrate having a first region and a second region; a plurality of first transistors provided in the first region; a plurality of second transistors provided in the second region, the plurality of second transistors being electrically coupled to the plurality of first transistors, respectively, and a breakdown-voltage of the second transistor being lower than a breakdown-voltage of the first transistor. A plurality of joint metals are provided above the first region, the plurality of joint metals being electrically coupled to the plurality of first transistors, respectively. A plurality of bit lines are provided in an upper layer of the plurality of joint metals, the plurality of bit lines being coupled to the plurality of joint metals, respectively; and a plurality of memory cells are provided in an upper layer of the plurality of bit lines, the plurality of memory cells being coupled to the plurality of bit lines, respectively.

公开(公告)号：US11875851B2

公开(公告)日：2024-01-16

申请号：US18080524

申请日：2022-12-13

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Maejima

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/32

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  G11C16/32

Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

公开(公告)号：US11727993B2

公开(公告)日：2023-08-15

申请号：US17864674

申请日：2022-07-14

Applicant: Kioxia Corporation

Inventor： Hiroshi Maejima

IPC: G11C16/04 ,  G11C16/10 ,  G11C5/02 ,  G11C5/06 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3422

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

公开(公告)号：US11705443B2

公开(公告)日：2023-07-18

申请号：US17012111

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Hiroshi Maejima ,  Katsuaki Isobe ,  Nobuaki Okada ,  Hiroshi Nakamura ,  Takahiro Tsurudo

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.