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    Power amplifier
    21.
    发明授权
    Power amplifier 失效
    功率放大器

    公开(公告)号：US07619470B2

    公开(公告)日：2009-11-17

    申请号：US11687770

    申请日：2007-03-19

    Applicant: Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya ,  Hideyuki Funaki

    Inventor： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya ,  Hideyuki Funaki

    IPC: H03F3/217

    CPC classification number: H03F3/2176 ,  H03F1/02 ,  H03F3/245 ,  H03F2200/366 ,  H03F2200/391 ,  H03F2203/21178 ,  H03G1/0088

    Abstract: A power amplifier includes: a plurality of field effect transistors connected in parallel and each having a first and second ends, the first end being connected to ground; an amplifying unit which includes at least one of an inductor, a capacitor and a band pass filter and has a third and fourth ends, the third end being connected to the second ends of the field effect transistors, and the fourth end outputting an amplified output signal; and an amplitude controller which sends control signals respectively to gates of the field effect transistors to turn on or off the field effect transistors based on an address signal for performing selection on the field effect transistors and a clock signal. Channel widths of the field effect transistors are different from each other.

    Abstract translation: 功率放大器包括：多个并联连接的场效应晶体管，每个具有第一和第二端，所述第一端连接到地; 放大单元，其包括电感器，电容器和带通滤波器中的至少一个，并具有第三和第四端，第三端连接到场效应晶体管的第二端，第四端输出放大的输出 信号; 以及幅度控制器，其基于用于对场效应晶体管进行选择的地址信号和时钟信号，分别向场效应晶体管的栅极发送控制信号以导通或关闭场效应晶体管。 场效应晶体管的沟道宽度彼此不同。

    SEMICONDUCTOR DEVICE
    22.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090134430A1

    公开(公告)日：2009-05-28

    申请号：US12276787

    申请日：2008-11-24

    Applicant: Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya

    Inventor： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya

    IPC: H01L27/105

    CPC classification number: H01L27/088 ,  H01L23/4824 ,  H01L27/0207 ,  H01L27/105 ,  H01L29/1033 ,  H01L29/41758 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A semiconductor device includes a substrate including an element region having a polygonal shape defined by a plurality of edges, and an isolation region surrounding the element region, and a plurality of gate electrodes provided on the substrate, crossing the element region, arranged in parallel with each other, and electrically connected with each other, wherein at least one of the edges does not cross any of the gate electrodes, and is not parallel to the gate electrodes.

    Abstract translation: 半导体器件包括：衬底，其包括具有由多个边缘限定的多边形形状的元件区域和围绕该元件区域的隔离区域;以及多个栅电极，设置在该衬底上，与该元件区域交叉，与该 彼此电连接，其中至少一个边缘不与任何栅电极交叉，并且不平行于栅电极。

    Power amplifier and transmission and reception system
    23.
    发明授权
    Power amplifier and transmission and reception system 有权
    功率放大器和发射和接收系统

    公开(公告)号：US07508268B2

    公开(公告)日：2009-03-24

    申请号：US11857737

    申请日：2007-09-19

    Applicant: Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Hideyuki Funaki

    Inventor： Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Hideyuki Funaki

    IPC: H03F3/68

    CPC classification number: H03F3/604 ,  H01L21/823425 ,  H01L27/088 ,  H03F1/3205 ,  H03F3/16 ,  H03F3/607 ,  H03F3/72 ,  H03F2200/108 ,  H03F2200/451 ,  H03F2200/468 ,  H03F2200/543 ,  H03F2200/78 ,  H03F2203/7236

    Abstract: A power amplifier includes: a first multi-finger FET formed on a semiconductor substrate; a second multi-finger FET formed on the semiconductor substrate; a first temperature detector which detects a channel temperature of the first FET; a second temperature detector which detects a channel temperature of the second FET; a third temperature detector which detects a temperature of the semiconductor substrate; a first detection circuit detecting a difference between an output of the first temperature detector and an output of the third temperature detector and converting the difference to thermoelectromotive force; a second detection circuit detecting a difference between an output of the second temperature detector and the output of the third temperature detector and converting the difference to thermoelectromotive force; and a comparator comparing outputs of the first and second detection circuits with each other to turn on one of the first and second switches and turn off the other.

    Abstract translation: 功率放大器包括：形成在半导体衬底上的第一多指FET; 形成在半导体衬底上的第二多指FET; 第一温度检测器，其检测第一FET的通道温度; 第二温度检测器，其检测第二FET的通道温度; 第三温度检测器，其检测半导体衬底的温度; 第一检测电路，检测第一温度检测器的输出和第三温度检测器的输出之间的差异，并将差值转换为热电动势; 第二检测电路，检测第二温度检测器的输出与第三温度检测器的输出之间的差异，并将差值转换为热电动势; 以及比较器，将第一和第二检测电路的输出彼此进行比较，以打开第一和第二开关中的一个并且关闭另一个。

    Receiver and Wireless Communication Apparatus
    26.
    发明申请
    Receiver and Wireless Communication Apparatus 失效
    接收机和无线通信设备

    公开(公告)号：US20080254756A1

    公开(公告)日：2008-10-16

    申请号：US11568365

    申请日：2006-09-25

    Applicant: Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

    Inventor： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

    IPC: H04B1/16 ,  H04B1/38

    CPC classification number: H04L27/2272 ,  H03C3/0966 ,  H03D3/242 ,  H04B1/38 ,  H04L27/2273 ,  H04L2027/0016 ,  H04L2027/0022 ,  H04L2027/0055 ,  H04W56/00 ,  H04W88/02 ,  Y02D70/1222 ,  Y02D70/40

    Abstract: A receiver has a first voltage control oscillator configured to generate a first oscillation signal, a second voltage control oscillator configured to generate a second oscillation signal having a first phase, a first phase comparator configured to detect a phase difference between the first and second oscillation signals, a demodulator configured to perform demodulation processing of the received signal and to generate timing information of a second phase included in the first oscillation signal, a second phase comparator configured to detect the phase difference between the first and second oscillation signals, and a first control voltage generator configured to generate a first control voltage for controlling a phase and a frequency of the second voltage control oscillator based on the phase difference detected by the second phase comparator.

    Abstract translation: 一种接收器具有：第一电压控制振荡器，被配置为产生第一振荡信号;第二压控振荡器，被配置为产生具有第一相位的第二振荡信号;第一相位比较器，被配置为检测第一和第二振荡信号之间的相位差; 解调器，被配置为执行所述接收信号的解调处理并生成包括在所述第一振荡信号中的第二相位的定时信息;第二相位比较器，被配置为检测所述第一和第二振荡信号之间的相位差;以及第一控制 电压发生器被配置为基于由第二相位比较器检测的相位差产生用于控制第二压控振荡器的相位和频率的第一控制电压。

    Method of forming copper wire
    29.
    发明授权
    Method of forming copper wire 有权
    铜线形成方法

    公开(公告)号：US07144812B2

    公开(公告)日：2006-12-05

    申请号：US10748254

    申请日：2003-12-31

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/44

    CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76858 ,  H01L21/76867

    Abstract: Cu is nitrided to form a nitride of Cu 5 on a Cu wiring layer 1. A diffusion base material layer 6 used as a diffusion source and a barrier metal layer 7, which are interdiffused with Cu, are formed on the nitride of Cu 5. With heat treatment, the Cu wiring layer 1 and the diffusion base material layer 6 are interdiffused to form an alloy layer of Cu 8 between the Cu wiring layer 1 and the barrier metal layer 7.

    Abstract translation: Cu在Cu布线层1上被氮化以形成Cu 5的氮化物。 在Cu 5的氮化物上形成有用作扩散源的扩散基材层6和与Cu相互扩散的阻挡金属层7。 通过热处理，Cu配线层1和扩散基材层6相互扩散，在Cu配线层1和阻挡金属层7之间形成Cu 8的合金层。

    Hybrid memory device and method for manufacturing the same
    30.
    发明申请
    Hybrid memory device and method for manufacturing the same 失效
    混合存储装置及其制造方法

    公开(公告)号：US20060065917A1

    公开(公告)日：2006-03-30

    申请号：US11228188

    申请日：2005-09-19

    Applicant: Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

    Inventor： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

    IPC: H01L29/94

    CPC classification number: H01L27/11502 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/11507

    Abstract: A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

    Abstract translation: 一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层 覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。

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