公开(公告)号：US20120286353A1

公开(公告)日：2012-11-15

申请号：US13106852

申请日：2011-05-12

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.

摘要翻译： 公开了一种沟槽MOS结构。 沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 沟槽栅极部分地设置在掺杂区域中。 沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。 两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

公开(公告)号：US08252684B1

公开(公告)日：2012-08-28

申请号：US13118480

申请日：2011-05-30

申请人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3081 ,  H01L21/3212

摘要： A method of forming a trench by a silicon-containing mask is provided in the present invention. The method includes providing a substrate covered with a silicon-containing mask. Then, anti-etch dopants are implanted into the silicon-containing mask to transform the silicon-containing mask into an etching resist mask. Later, the substrate and the etching resist mask are patterned to form at least one trench. Next, a silicon-containing layer is formed to fill into the trench. Finally, the silicon-containing layer is etched by taking the etching resist mask as a mask.

摘要翻译： 在本发明中提供了通过含硅掩模形成沟槽的方法。 该方法包括提供用含硅掩模覆盖的基底。 然后，将抗蚀刻掺杂剂注入到含硅掩模中以将含硅掩模转变成抗蚀剂掩模。 然后，对衬底和抗蚀剂掩模进行构图以形成至少一个沟槽。 接下来，形成含硅层以填充到沟槽中。 最后，通过将抗蚀剂掩模作为掩模来蚀刻含硅层。

公开(公告)号：US06774007B2

公开(公告)日：2004-08-10

申请号：US10244988

申请日：2002-09-17

申请人： Hsien-Wen Liu ,  Hui Min Mao ,  Yi-Nan Chen ,  Yi-Chen Chen

发明人： Hsien-Wen Liu ,  Hui Min Mao ,  Yi-Nan Chen ,  Yi-Chen Chen

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method of fabricating shallow trench isolation. In the method, a refill step of oxide layer and a step of forming a sacrificial layer on the semiconductor substrate are applied after filling insulating layer into the shallow trenches. The purpose of the steps is to protect the oxide layer on the semiconductor substrate and the corner of the shallow trenches, used to isolate the STI.

摘要翻译： 一种制造浅沟槽隔离的方法。 在该方法中，在将绝缘层填充到浅沟槽中之后，施加氧化物层的再填充步骤和在半导体衬底上形成牺牲层的步骤。 步骤的目的是保护用于隔离STI的半导体衬底上的氧化物层和浅沟槽的角部。

公开(公告)号：US06716696B2

公开(公告)日：2004-04-06

申请号：US10206733

申请日：2002-07-26

申请人： Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84

摘要： A method of forming a bottle-shaped trench in a semiconductor substrate. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. An oxide film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench with a diluted ammonia solution as the etchant to form a bottle-shaped trench followed by removal of the oxide film.

摘要翻译： 一种在半导体衬底中形成瓶形沟槽的方法。 首先，选择性地蚀刻半导体衬底以形成沟槽，其中沟槽具有顶部和底部。 然后在沟槽的顶部上形成氧化膜。 接下来，半导体衬底通过沟槽的底部用稀释的氨溶液作为蚀刻剂进行蚀刻，以形成瓶状沟槽，随后除去氧化物膜。

公开(公告)号：US06713341B2

公开(公告)日：2004-03-30

申请号：US10162156

申请日：2002-06-03

申请人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Hsin-Chuan Tsai

发明人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Hsin-Chuan Tsai

IPC分类号： H01L218242

CPC分类号： H01L29/66181

摘要： A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

摘要翻译： 一种在半导体衬底中形成瓶形沟槽的方法。 该方法适用于DRAM的电容器的形成。 首先，选择性地蚀刻半导体衬底以形成沟槽，其中沟槽具有顶部和底部。 然后在沟槽的顶部上形成氮化物膜。 接下来，通过作为蚀刻剂的过氧化氢和氢氟酸的溶液，通过沟槽的底部蚀刻半导体衬底，以形成瓶状沟槽，随后除去氮化物膜。

公开(公告)号：US06426271B2

公开(公告)日：2002-07-30

申请号：US09790493

申请日：2001-02-23

申请人： Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31662

摘要： The present invention provides a method of rounding the corner of the shallow trench isolation region, comprising the steps of: etching silicon substrate using a patterned mask layer and a pad oxide layer as an etch mask to form a trench in the silicon substrate, then removing part of the pad oxide layer, forming silicon dioxide on the surface of the silicon substrate in the trench, then removing part of the pad oxide layer and the silicon dioxide on the surface of the silicon substrate in the trench, repeating the step of oxidizing the surface of the silicon substrate and removing part of the pad oxide layer and silicon dioxide to round the corner of the trench, then performing the subsequent steps to form the shallow trench isolation region.

公开(公告)号：US09054131B2

公开(公告)日：2015-06-09

申请号：US13281293

申请日：2011-10-25

申请人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/66666 ,  H01L21/823487 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.

摘要翻译： 公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域， 以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

公开(公告)号：US08759907B2

公开(公告)日：2014-06-24

申请号：US13094796

申请日：2011-04-26

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/108 ,  H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

摘要： A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

摘要翻译： 提供一种形成掩埋位线的方法。 提供衬底并且在衬底中限定线状沟槽区域。 在基板的线状沟槽区域中形成线状沟槽。 线状沟槽包括侧壁表面和底部表面。 然后，将线状沟槽的底面加宽，形成弯曲的底面。 接下来，在与该弯曲底面相邻的基板上形成掺杂区域。 最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

公开(公告)号：US08758984B2

公开(公告)日：2014-06-24

申请号：US13103108

申请日：2011-05-09

申请人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/70

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/28132

摘要： A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.

摘要翻译： 一种形成栅极导体结构的方法。 提供了具有栅电极层的基板。 形成覆盖栅电极层的多层硬掩模。 多层硬掩模包括第一硬掩模，第二硬掩模和第三硬掩模。 在多层硬掩模上形成光刻胶图形。 执行第一蚀刻工艺以蚀刻第三硬掩模，使用光致抗蚀剂图案作为第一蚀刻抗蚀剂，由此形成图案化的第三硬掩模。 执行第二蚀刻工艺以蚀刻第二硬掩模和第一硬掩模，使用图案化的第三硬掩模作为第二蚀刻抗蚀剂，由此形成图案化的第一硬掩模。 执行第三蚀刻工艺以蚀刻栅极电极层的层，使用图案化的第一硬掩模作为第三蚀刻抗蚀剂。

公开(公告)号：US08476764B2

公开(公告)日：2013-07-02

申请号：US13235491

申请日：2011-09-18

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05085 ,  H01L2224/05095 ,  H01L2224/05624

摘要： A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.

摘要翻译： 焊盘结构包括其上具有包括至少最上面的IMD层的多个金属间电介质（IMD）层的半导体衬底; 可焊接金属焊盘层，其设置在焊盘形成区域内的最上层IMD层的表面上; 覆盖可焊接金属焊盘层的周边和最上面的IMD层的表面的钝化层; 以及多个通孔插塞，其设置在焊盘形成区域的环形区域内的最上层的IMD层中，其中通孔插塞不形成在焊盘形成区域的中心区域中。