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    SINGLE SPACER PROCESS FOR MULTIPLYING PITCH BY A FACTOR GREATER THAN TWO AND RELATED INTERMEDIATE IC STRUCTURES
    22.
    发明申请
    SINGLE SPACER PROCESS FOR MULTIPLYING PITCH BY A FACTOR GREATER THAN TWO AND RELATED INTERMEDIATE IC STRUCTURES 有权
    通过两个和相关的中间IC结构的因子进行多路复用的单个间隔处理

    公开(公告)号：US20140038416A1

    公开(公告)日：2014-02-06

    申请号：US14053346

    申请日：2013-10-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David H. Wells ,  Mirzafer K. Abatchev

    IPC: H01L21/308

    CPC classification number: H01L23/5386 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/942 ,  Y10S438/946 ,  Y10S438/947 ,  H01L2924/00

    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

    Abstract translation: 提供了用于将音调乘以大于2的因子的单间隔物处理。 在一个实施例中，n，其中n≥2，在衬底上形成层叠的心轴层，n层​​中的每一层包括基本上彼此平行的多个心轴。 层n上的心轴结束并平行于n-1层的心轴，层n的相邻心轴之间的距离大于n-1层相邻心轴之间的距离。 间隔件同时形成在心轴的侧壁上。 蚀刻掉心轴的裸露部分，并且由间隔物限定的线的图案被转移到基底。

    Sparse piers for three-dimensional memory arrays
    23.
    发明授权
    Sparse piers for three-dimensional memory arrays 有权

    公开(公告)号：US12302766B2

    公开(公告)日：2025-05-13

    申请号：US17656280

    申请日：2022-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Enrico Varesi ,  David H. Wells ,  Paolo Fantini ,  Lorenzo Fratin

    IPC: H10B63/10 ,  G11C13/00 ,  H10B63/00 ,  H10D64/01 ,  H10N70/00 ,  H01L21/02

    Abstract: Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.

    MEMORY DEVICES INCLUDING STAIRCASE STRUCTURES
    24.
    发明申请
    MEMORY DEVICES INCLUDING STAIRCASE STRUCTURES 有权

    公开(公告)号：US20250132248A1

    公开(公告)日：2025-04-24

    申请号：US19005952

    申请日：2024-12-30

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Richard J. Hill ,  Umberto M. Meotto ,  Matthew Thorum

    IPC: H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

    METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MICROELECTRONIC DEVICES
    25.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MICROELECTRONIC DEVICES 有权

    公开(公告)号：US20240373636A1

    公开(公告)日：2024-11-07

    申请号：US18621738

    申请日：2024-03-29

    Applicant: Micron Technology, Inc.

    Inventor： Matthew J. King ,  David H. Wells ,  Yiping Wang ,  Mojtaba Asadirad ,  Harsh Narendrakumar Jain

    IPC: H10B43/27 ,  H10B41/27

    Abstract: A method of forming a microelectronic device comprises forming a preliminary stack structure over a source structure. The preliminary stack structure comprises a vertically alternating sequence of insulative material and sacrificial material arranged in preliminary tiers. The method comprises forming a staircase structure having steps comprising edges of at least some of the preliminary tiers of the preliminary stack structure, forming implant regions within exposed portions of the sacrificial material at the steps of the staircase structure, forming openings extending through the preliminary stack structure to the source structure and within a horizontal area of the staircase structure, replacing portions of the sacrificial material with conductive structures, forming strapping structures comprising conductive material, at locations vacated by the implant regions, laterally adjacent to the conductive structures at the steps of the staircase structure, and forming conductive contacts within the openings. Additional methods and microelectronic devices are also described.

    Electronic devices comprising a source below memory cells and related systems
    29.
    发明授权
    Electronic devices comprising a source below memory cells and related systems 有权

    公开(公告)号：US10923494B2

    公开(公告)日：2021-02-16

    申请号：US16194946

    申请日：2018-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Darwin A. Clampitt ,  David H. Wells ,  John D. Hopkins ,  Kevin Y. Titus

    IPC: H01L27/11582 ,  H01L27/11521 ,  H01L29/08 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11556 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L21/28 ,  H01L29/45 ,  H01L21/321

    Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.

    Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array
    30.
    发明申请
    Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array 审中-公开

    公开(公告)号：US20190198320A1

    公开(公告)日：2019-06-27

    申请号：US15903280

    申请日：2018-02-23

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Anish A. Khandekar ,  Kunal Shrotri ,  Jie Li

    IPC: H01L21/02 ,  H01L27/115

    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

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