公开(公告)号：US20150206906A1

公开(公告)日：2015-07-23

申请号：US14599886

申请日：2015-01-19

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Haitao Liu ,  Zhenyu Lu

IPC: H01L27/12 ,  H01L29/04 ,  H01L21/285 ,  H01L21/02 ,  H01L21/223 ,  H01L21/324 ,  H01L27/115 ,  H01L29/16

CPC classification number: H01L27/1222 ,  H01J37/32412 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02595 ,  H01L21/2236 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/324 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66757

Abstract: Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled.

Abstract translation: 公开了形成薄膜晶体管和存储器的方法。 在一种这样的方法中，多晶硅是掺杂氢的等离子体以形成掺杂的多晶硅。 然后将掺杂的多晶硅退火。 氢等离子体掺杂和退火是去耦合的。

公开(公告)号：US20140197416A1

公开(公告)日：2014-07-17

申请号：US13739679

申请日：2013-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shu Qin ,  Haitao Liu ,  Zhenyu Lu

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1222 ,  H01J37/32412 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02595 ,  H01L21/2236 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/324 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66757

Abstract: Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled.

Abstract translation: 公开了形成薄膜晶体管和存储器的方法。 在一种这样的方法中，多晶硅是掺杂氢的等离子体以形成掺杂的多晶硅。 然后将掺杂的多晶硅退火。 氢等离子体掺杂和退火是去耦合的。

公开(公告)号：US11949022B2

公开(公告)日：2024-04-02

申请号：US17678971

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A. Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L29/788 ,  H01L21/285 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/788 ,  H01L21/28518 ,  H01L23/535 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US11665893B2

公开(公告)日：2023-05-30

申请号：US15255967

申请日：2016-09-02

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Andrew Bicksler ,  Yongjun Jeff Hu ,  Haitao Liu

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11524 ,  H01L23/528 ,  H01L29/45

CPC classification number: H01L27/11556 ,  H01L23/5283 ,  H01L27/11524 ,  H01L29/456 ,  H01L29/66825 ,  H01L29/7926

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

公开(公告)号：US11626424B2

公开(公告)日：2023-04-11

申请号：US17397338

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11563

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US10651315B2

公开(公告)日：2020-05-12

申请号：US13716287

申请日：2012-12-17

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/528 ,  H01L23/532 ,  H01L27/1157 ,  H01L21/285 ,  H01L23/535 ,  H01L29/66 ,  H01L29/792

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US20180315766A1

公开(公告)日：2018-11-01

申请号：US16028111

申请日：2018-07-05

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/285 ,  H01L21/311 ,  H01L29/51 ,  H01L29/10 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/513 ,  H01L29/66825

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20160284728A1

公开(公告)日：2016-09-29

申请号：US15174478

申请日：2016-06-06

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/115 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract translation: 一些实施例包括具有多层存储器单元和相关控制门的装置和方法。 一种方法包括形成具有交替的导体材料和电介质材料的第一甲板和包含延伸穿过导体材料和电介质材料的材料的孔。 所述方法还可以包括在所述孔的扩大部分中形成牺牲材料并在所述第一甲板上形成第二层记忆单元。 描述附加的装置和方法。

公开(公告)号：US20210366931A1

公开(公告)日：2021-11-25

申请号：US17397338

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20200227427A1

公开(公告)日：2020-07-16

申请号：US16834291

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.