公开(公告)号：US06836398B1

公开(公告)日：2004-12-28

申请号：US10284769

申请日：2002-10-31

申请人： Ramkumar Subramanian ,  Jane V. Oglesby ,  Minh Van Ngo ,  Mark S. Chang ,  Sergey D. Lopatin ,  Angela T. Hui ,  Christopher F. Lyons ,  Patrick K. Cheung ,  Ashok M. Khathuria

发明人： Ramkumar Subramanian ,  Jane V. Oglesby ,  Minh Van Ngo ,  Mark S. Chang ,  Sergey D. Lopatin ,  Angela T. Hui ,  Christopher F. Lyons ,  Patrick K. Cheung ,  Ashok M. Khathuria

IPC分类号： H01G435

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L21/3212 ,  H01L27/285 ,  H01L28/75

摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.

摘要翻译： 本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。 本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。 在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。 还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。 因此，钝化层与用于形成电极的还原CMP工艺结合形成。

公开(公告)号：US06642148B1

公开(公告)日：2003-11-04

申请号：US10126326

申请日：2002-04-19

申请人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

发明人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

IPC分类号： H01L21302

CPC分类号： H01L29/6659 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/11568

摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

摘要翻译： 本发明一般涉及一种在半导体衬底内形成渐变结的方法。 在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。 半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。 第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。 然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。

公开(公告)号：US06400030B1

公开(公告)日：2002-06-04

申请号：US09583817

申请日：2000-05-30

申请人： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

发明人： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/76802

摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.

摘要翻译： 具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。 在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。 通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。 第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。 第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。 阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

公开(公告)号：US5945352A

公开(公告)日：1999-08-31

申请号：US994710

申请日：1997-12-19

申请人： Hung-Sheng Chen ,  Mark S. Chang

发明人： Hung-Sheng Chen ,  Mark S. Chang

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76237 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76232 ,  Y10S148/05

摘要： The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying thickness. The thickest areas of the etch barrier are located on the edges of trench structures and slow the etch process in the underlying substrate. The thinner regions of the etch barrier do not impede the etch process to as great an extent. This etch rate differential causes a sloped trench wall profile. The isolation trenches are completed by filling the surface with dielectric materials then planarizing.

摘要翻译： 本发明提供一种用于在半导体晶片中制造具有倾斜壁的浅隔离沟槽的方法。 该方法使用共形多晶硅层在半导体衬底中的沟槽区域上形成蚀刻势垒。 该蚀刻屏障具有不同厚度的区域。 蚀刻阻挡层的最厚区域位于沟槽结构的边缘上并减缓下面的衬底中的蚀刻过程。 蚀刻阻挡层的较薄区域不会将蚀刻过程阻碍到很大的程度。 该蚀刻速率差异导致倾斜的沟槽壁轮廓。 通过用介电材料填充表面然后平坦化来完成隔离沟槽。

公开(公告)号：US5550405A

公开(公告)日：1996-08-27

申请号：US360856

申请日：1994-12-21

申请人： Robin W. Cheung ,  Mark S. Chang

发明人： Robin W. Cheung ,  Mark S. Chang

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53242 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S148/10 ,  Y10S148/106 ,  Y10S438/95 ,  Y10S438/951

摘要： The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.

摘要翻译： 接触金属线的半导体器件中的互连包括诸如铜，金，银或铂的低电阻金属，并且由具有低介电常数的材料例如苯并环丁烯或其衍生物分离。 使用三层抗蚀剂结构以及剥离工艺来形成互连。 低介电常数材料为低电阻金属的扩散提供扩散阻挡层。 三层抗蚀剂包括可溶解聚合物的第一层，硬掩模材料的第二层和抗蚀剂材料的第三层。 所得到的结构提供了具有增加的速度和易于制造的集成电路。

公开(公告)号：US4370405A

公开(公告)日：1983-01-25

申请号：US248927

申请日：1981-03-30

申请人： Michael M. O'Toole ,  En-Den D. Liu ,  Mark S. Chang

发明人： Michael M. O'Toole ,  En-Den D. Liu ,  Mark S. Chang

IPC分类号： H01L21/302 ,  G03F7/09 ,  H01L21/027 ,  H01L21/30 ,  H01L21/3065 ,  G03C5/00

CPC分类号： G03F7/094 ,  H01L21/30

摘要： An improved photoetch technique is presented of the multilayer resist type wherein a thin top layer of resist and a thick planarizing layer are deposited on a substrate and the thin layer is exposed and developed to produce a patterned resist layer. The improvement involves dissolving a suitable dye in a layer between the thin top layer and the substrate. The dye is preferably selected to absorb light of the wavelengths used to expose the top layer but does not interfere with processing of the other layers.

摘要翻译： 提出了一种改进的光刻技术，其中抗蚀剂的薄顶层和厚的平坦化层沉积在衬底上，并且薄层被曝光和显影以产生图案化的抗蚀剂层。 该改进涉及将合适的染料溶解在薄顶层和基底之间的层中。 优选选择染料以吸收用于暴露顶层的波长的光，但不影响其它层的处理。

公开(公告)号：US08183619B1

公开(公告)日：2012-05-22

申请号：US09539458

申请日：2000-03-30

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

公开(公告)号：US06753247B1

公开(公告)日：2004-06-22

申请号：US10285183

申请日：2002-10-31

申请人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

发明人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

IPC分类号： H01L214763

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L27/285

摘要： A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. A wordline is then formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via. A memory device formed in accordance with the disclosed methodology includes a top electrode formed over an organic polymer layer, a conductive layer under the organic polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline formed over the dielectric material such that the top electrode is connected to the wordline by way of the via.

摘要翻译： 公开了一种用于形成存储单元的方法，其中在导电层上形成有机聚合物层，并且在有机聚合物层上形成电极层。 将第一通孔蚀刻到电极和有机聚合物层中，并且将电介质材料施加到堆叠上以至少填充在第一通孔中。 然后将第二通道蚀刻到电介质材料中，以暴露并使电极层可用作顶部电极。 然后在电介质材料上形成字线，使得顶部电极通过第二通孔连接到字线。 根据所公开的方法形成的存储器件包括形成在有机聚合物层上的顶部电极，有机聚合物层下面的导电层，由电介质材料限定并位于顶部电极之上的通孔，以及形成在上部电极上的字线 电介质材料，使得顶部电极通过通孔连接到字线。

公开(公告)号：US06610580B1

公开(公告)日：2003-08-26

申请号：US09563179

申请日：2000-05-02

申请人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

发明人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

IPC分类号： H01L2176

CPC分类号： H01L27/11521 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/11517

摘要： In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back. Through the use of the preferred embodiment of the present invention, a shallow trench isolation process is implemented as opposed to LOCOS process, thereby reducing the occurrence of polyl stringers in the channel area. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent regions is substantially reduced.

摘要翻译： 在本发明的第一方面，公开了一种闪存阵列。 闪存阵列包括包含有源区的衬底，其中有源区由氮化物层限定，氮化物层包括顶表面。 闪存阵列还包括衬底中的浅沟槽，每个浅沟槽包括一层氧化物，氧化层具有顶表面，其中氧化层的顶表面和氮化层的顶表面 在基本相同的平面和通道区域上，其中通道区域中多边形桁条的出现被大大减少。 在本发明的第二方面中，公开了一种用于制造闪存阵列的方法和系统。 该方法包括以下步骤：在衬底上提供氮化物层，在衬底中形成沟槽，然后在沟槽中生长一层氧化物。 最后，氧化层被抛光。 通过使用本发明的优选实施例，与LOCOS工艺相反，实现了浅沟槽隔离工艺，从而减少了通道区域中多边形的发生。 因此，相邻区域之间不需要的电短路径的发生显着减少。

公开(公告)号：US06566230B1

公开(公告)日：2003-05-20

申请号：US10032630

申请日：2001-12-27

申请人： Harpreet K. Sachar ,  Unsoon Kim ,  Mark S. Chang ,  Chih Y. Yang ,  Jayendra D. Bhakta

发明人： Harpreet K. Sachar ,  Unsoon Kim ,  Mark S. Chang ,  Chih Y. Yang ,  Jayendra D. Bhakta

IPC分类号： H03L2176

CPC分类号： H01L21/76224

摘要： A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.

摘要翻译： 公开了一种用于在半导体器件制造期间执行沟槽隔离的方法。 该方法包括图案化硬掩模以限定衬底上的有源区和隔离区，以及沿着硬掩模的边缘形成间隔物。 然后使用间隔件作为掩模在衬底中形成沟槽，从而增加衬底在有源区域下的宽度并增加器件的Weff。