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51 条记录 (耗时 0.024 秒)

    Semiconductor memory circuit
    21.
    发明授权
    Semiconductor memory circuit 失效
    半导体存储电路

    公开(公告)号：US06914840B2

    公开(公告)日：2005-07-05

    申请号：US10790135

    申请日：2004-03-02

    申请人： Masashi Agata

    发明人： Masashi Agata

    IPC分类号： H01L27/108 ,  G11C7/12 ,  G11C7/14 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099 ,  H01L21/8242 ,  G11C7/02

    CPC分类号： H01L27/10897 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4094 ,  G11C11/4099

    摘要： Data reading speed of a DRAM is enhanced without causing an increase in the power consumption and in the chip area. To that end, when data is read, a pair of bit lines is precharged to a GND level, while a dummy cell is charged at a power supply voltage. Immediately after a word line and a dummy word line are activated and their respective potentials are increased by the threshold voltage of an access transistor, a main capacitor and a dummy capacitor are electrically connected to the bit lines, thereby allowing the data to fade in. The resultant potential difference between the pair of bit lines is detected and amplified by a sense amplifier, thereby enabling the data to be read. The capacitance of the dummy capacitor is about half of that of the main capacitor, so that the dummy capacitor can be precharged at the power supply voltage.

    摘要翻译： 增强DRAM的数据读取速度，而不会增加功耗和芯片区域。 为此，当读取数据时，一对位线被预充电到GND电平，而虚设单元以电源电压被充电。 在字线和虚拟字线被激活并且它们各自的电位被存取晶体管的阈值电压增加之后，主电容器和虚拟电容器电连接到位线，从而允许数据淡入。 一对位线之间的合成电位差由读出放大器检测和放大，从而使数据能被读取。 虚拟电容器的电容大约是主电容器的电容的一半，这样虚拟电容器可以在电源电压下进行预充电。

    Semiconductor memory device
    22.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5629903A

    公开(公告)日：1997-05-13

    申请号：US632826

    申请日：1996-04-16

    申请人： Masashi Agata

    发明人： Masashi Agata

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/10 ,  G11C11/408 ,  H01L27/10 ,  G11C8/00

    CPC分类号： G11C7/1072 ,  G11C8/10

    摘要： This invention discloses a synchronous DRAM. An address counter provides a column address of eight bits. The low-order four bits of the column address are assigned to a first column predecoder while the high-order four bits are assigned to a second column predecoder. The first column predecoder provides first predecode signals which are activated in synchronization with a clock leading edge of an internal clock signal and deactivated in synchronization with a clock trailing edge subsequent to the clock leading edge. The second column predecoder provides second predecode signals which make a transition in synchronization with the clock trailing edge. A column decoder sequentially activates column-select lines of a memory cell array according to the AND obtained from all combinations of the first predecode signals and the second predecode signals. Fast, low power column-select line activation is accomplished accordingly.

    摘要翻译： 本发明公开了一种同步DRAM。 地址计数器提供8位的列地址。 列地址的低位四位被分配给第一列预解码器，而高位四位被分配给第二列预解码器。 第一列预解码器提供与内部时钟信号的时钟前沿同步地激活的第一预解码信号，并且与时钟前沿之后的时钟后沿同步地去激活。 第二列预解码器提供与时钟后沿同步的第二预解码信号。 列解码器根据从第一预解码信号和第二预解码信号的所有组合获得的AND顺序激活存储器单元阵列的列选择行。 快速，低功率的列选择线激活相应地完成。

    Semiconductor storage device
    24.
    发明授权
    Semiconductor storage device 有权
    半导体存储设备

    公开(公告)号：US6137713A

    公开(公告)日：2000-10-24

    申请号：US420576

    申请日：1999-10-19

    申请人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

    发明人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/24 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/108 ,  G11C11/24 ,  G11C11/405 ,  G11C5/02 ,  G11C5/063 ,  H01L27/10885

    摘要： Over an active region with two bent portions on a semiconductor substrate, first and second word lines extend to cross these bent portions and to be vertically spaced apart from each other. Around at the center of the active region, a capacitor for storing data thereon and a capacitor contact are formed. A first bit line contact, which is connected to the active region, is formed on the opposite side to the capacitor contact across the first word line over the active region. A second bit line contact, which is also connected to the active region, is formed on the opposite side to the capacitor contact across the second word line over the active region. These first and second bit line contacts are provided substantially symmetrically about the center of the memory cell. In a pair of memory cells adjacent to each other along bit lines, one vertical end of the active region in one of the memory cells is continuous with an associated vertical end of the active region in the other memory cell. And each of the first and second bit line contacts is shared between an adjacent pair of memory cells.

    摘要翻译： 在半导体衬底上具有两个弯曲部分的有源区域上，第一和第二字线延伸以跨越这些弯曲部分并且彼此垂直间隔开。 在有源区域的中心附近形成用于存储数据的电容器和电容器触点。 连接到有源区域的第一位线触点形成在跨过有源区域的跨第一字线的电容器触点的相反侧。 还连接到有源区的第二位线触点形成在跨过有源区的跨越第二字线的电容器触点的相反侧。 这些第一和第二位线触点基本上围绕存储器单元的中心对称地设置。 在沿着位线彼此相邻的一对存储单元中，一个存储单元中的有源区的一个垂直端与另一个存储单元中的有源区的相关联的垂直端连续。 并且第一和第二位线触点中的每一个在相邻的一对存储单元之间共享。

    Timing signal generation circuit
    25.
    发明授权
    Timing signal generation circuit 失效

    公开(公告)号：US5892384A

    公开(公告)日：1999-04-06

    申请号：US658931

    申请日：1996-05-31

    申请人： Toshio Yamada ,  Masashi Agata

    发明人： Toshio Yamada ,  Masashi Agata

    IPC分类号： G11C7/00 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K3/02 ,  H03K3/10 ,  H03K5/13 ,  H03K5/131 ,  H03K5/19 ,  H04L7/00 ,  H03H11/26

    CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286

    摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.

    Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory
    26.
    发明授权
    Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
    数据传输电路，数据线驱动电路，放大电路，半导体集成电路和半导体存储器

    公开(公告)号：US5680366A

    公开(公告)日：1997-10-21

    申请号：US573133

    申请日：1995-12-15

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  H03K3/26

    CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

    摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

    Semiconductor memory device
    28.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06751116B2

    公开(公告)日：2004-06-15

    申请号：US10233486

    申请日：2002-09-04

    申请人： Naoki Kuroda ,  Masashi Agata

    发明人： Naoki Kuroda ,  Masashi Agata

    IPC分类号： G11C1124

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281

    摘要： A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

    摘要翻译： 包括要访问的存储单元的第一晶体管，第一位线对，第一列选择开关和数据线对的路径的端口A与包括存储器单元的第二晶体管的路径的端口B交错 要被访问的第二位线对，第二列选择开关和数据线对在时钟的两个周期中。 读取放大器将从位线对传送的数据放大到数据线对，并在时钟的一个周期内将结果数据输出到输入/输出缓冲器。 输入/输出缓冲器在时钟的一个周期内将从读取放大器接收到的数据输出到外部。

    Timing signal generation circuit
    29.
    发明授权
    Timing signal generation circuit 失效
    定时信号发生电路

    公开(公告)号：US06285723B1

    公开(公告)日：2001-09-04

    申请号：US09513714

    申请日：2000-02-25

    申请人： Toshio Yamada ,  Masashi Agata

    发明人： Toshio Yamada ,  Masashi Agata

    IPC分类号： H04L700

    CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286

    摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.

    摘要翻译： 根据本发明的定时信号产生电路包括：延迟电路，用于在延迟时钟信号的同时传输输入时钟信号，延迟电路具有多个中间抽头，能够在延迟电路的相应位置输出时钟信号 ; 用于在延迟时钟信号的同时发送时钟信号的检测延迟电路，所述检测延迟电路具有能够在其检测延迟电路中的相应位置处输出时钟信号的多个中间抽头; 多个采样/保持电路，每个采样/保持电路均具有采样信号端子，采样信号端子连接到检测延迟电路的多个中间抽头中的相应的一个; 用于检测时钟信号的边沿的多个边界延迟电路，边界检测电路连接到取样/保持电路的各个输出端; 以及输出选择电路，用于经由根据由边界检测电路检测的时钟信号的边缘位置选择的多个中间抽头中的至少一个提取时钟信号，输出选择电路将提取的时钟信号作为定时输出 信号。

    Semiconductor memory device that can read out data faster than writing it
    30.
    发明授权
    Semiconductor memory device that can read out data faster than writing it 有权
    半导体存储器件可以比写入数据更快地读出数据

    公开(公告)号：US06229758B1

    公开(公告)日：2001-05-08

    申请号：US09662149

    申请日：2000-09-14

    申请人： Masashi Agata

    发明人： Masashi Agata

    IPC分类号： G11C800

    CPC分类号： G11C7/1072

    摘要： The semiconductor memory device of the invention includes: a data storage section for storing data thereon; a data write section for writing data on the storage section; and a data read section for reading out the data stored on the storage section. The read section generates a read clock signal responsive to an external clock signal, and the write section generates a write clock signal responsive to the external clock signal. And one cycle of the read clock signal is set shorter than one cycle of the write clock signal.

    摘要翻译： 本发明的半导体存储器件包括：数据存储部分，用于在其上存储数据; 用于在存储部分上写入数据的数据写入部分; 以及用于读出存储在存储部分上的数据的数据读取部分。 读取部分响应于外部时钟信号产生读取时钟信号，并且写入部分响应于外部时钟信号产生写入时钟信号。 读时钟信号的一个周期被设置为短于写时钟信号的一个周期。