公开(公告)号：US07416963B2

公开(公告)日：2008-08-26

申请号：US11182055

申请日：2005-07-15

申请人： Mitsuo Umemoto ,  Yoshio Okayama ,  Kazumasa Tanida ,  Hiroshi Terao ,  Yoshihiko Nemoto

发明人： Mitsuo Umemoto ,  Yoshio Okayama ,  Kazumasa Tanida ,  Hiroshi Terao ,  Yoshihiko Nemoto

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L29/40 ,  H01L23/52 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/05548

摘要： This invention offers a manufacturing method to reduce a manufacturing cost of a semiconductor device having a through-hole electrode by simplifying a manufacturing process and to enhance yield of the semiconductor device. A first insulation film is formed on a top surface of a semiconductor substrate. A part of the first insulation film is etched to form an opening in which a part of the semiconductor substrate is exposed. Then a pad electrode is formed in the opening and on the first insulation film. A second insulation film is formed on a back surface of the semiconductor substrate. Then a via hole having an aperture larger than the opening is formed. And a third insulation film is formed in the via hole and on the second insulation film. The third insulation film on a bottom of the via hole is etched to expose the pad electrode. After that, a through-hole electrode and a wiring layer are formed in the via hole. Finally, the semiconductor substrate is cut and separated into a plurality of semiconductor dice.

摘要翻译： 本发明提供了通过简化制造工艺并提高半导体器件的产量来降低具有通孔电极的半导体器件的制造成本的制造方法。 第一绝缘膜形成在半导体衬底的顶表面上。 蚀刻第一绝缘膜的一部分以形成半导体衬底的一部分露出的开口。 然后在开口和第一绝缘膜上形成焊盘电极。 第二绝缘膜形成在半导体衬底的背面上。 然后形成具有比开口大的孔的通孔。 并且在通孔和第二绝缘膜上形成第三绝缘膜。 对通孔的底部的第三绝缘膜进行蚀刻以露出焊盘电极。 之后，在通孔中形成通孔电极和布线层。 最后，将半导体衬底切割并分离成多个半导体管芯。

公开(公告)号：US07256497B2

公开(公告)日：2007-08-14

申请号：US11054603

申请日：2005-02-10

申请人： Koujiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama

发明人： Koujiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama

IPC分类号： H01L29/74 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/3025 ,  H01L2924/00014

摘要： This invention provides a semiconductor device that can minimize deterioration of electric characteristics of the semiconductor device while minimizing the amount of etching required. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a wiring layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the wiring layer.

摘要翻译： 本发明提供一种能够最小化所需蚀刻量的半导体器件的电特性的劣化最小化的半导体器件。 在本发明的半导体器件中，在半导体衬底的顶表面上形成由第一阻挡层和层叠在其上的铝层形成的焊盘电极层。 支撑衬底进一步附着在半导体衬底的顶表面上。 第二阻挡层形成在半导体衬底的背面和从半导体衬底的背面形成到第一阻挡层的通孔中。 此外，在通孔中形成布线层，以便完全填充通孔或不完全填充通孔。 在布线层上形成球状端子。

公开(公告)号：US20060033168A1

公开(公告)日：2006-02-16

申请号：US11182055

申请日：2005-07-15

申请人： Mitsuo Umemoto ,  Yoshio Okayama ,  Kazumasa Tanida ,  Hiroshi Terao ,  Yoshihiko Nemoto

发明人： Mitsuo Umemoto ,  Yoshio Okayama ,  Kazumasa Tanida ,  Hiroshi Terao ,  Yoshihiko Nemoto

IPC分类号： H01L29/76

CPC分类号： H01L21/76898 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/05548

摘要： This invention offers a manufacturing method to reduce a manufacturing cost of a semiconductor device having a through-hole electrode by simplifying a manufacturing process and to enhance yield of the semiconductor device. A first insulation film is formed on a top surface of a semiconductor substrate. A part of the first insulation film is etched to form an opening in which a part of the semiconductor substrate is exposed. Then a pad electrode is formed in the opening and on the first insulation film. A second insulation film is formed on a back surface of the semiconductor substrate. Then a via hole having an aperture larger than the opening is formed. And a third insulation film is formed in the via hole and on the second insulation film. The third insulation film on a bottom of the via hole is etched to expose the pad electrode. After that, a through-hole electrode and a wiring layer are formed in the via hole. Finally, the semiconductor substrate is cut and separated into a plurality of semiconductor dice.

摘要翻译： 本发明提供了通过简化制造工艺并提高半导体器件的产量来降低具有通孔电极的半导体器件的制造成本的制造方法。 第一绝缘膜形成在半导体衬底的顶表面上。 蚀刻第一绝缘膜的一部分以形成半导体衬底的一部分露出的开口。 然后在开口和第一绝缘膜上形成焊盘电极。 第二绝缘膜形成在半导体衬底的背面上。 然后形成具有比开口大的孔的通孔。 并且在通孔和第二绝缘膜上形成第三绝缘膜。 对通孔的底部的第三绝缘膜进行蚀刻以露出焊盘电极。 之后，在通孔中形成通孔电极和布线层。 最后，将半导体衬底切割并分离成多个半导体管芯。

公开(公告)号：US20050196957A1

公开(公告)日：2005-09-08

申请号：US11057413

申请日：2005-02-15

申请人： Koujiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama

发明人： Koujiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76898 ,  H01L2224/02372 ,  H01L2224/05548

摘要： This invention provides an etching method for preventing deformation of an opening without extremely lowering productivity. This invention has a process for bonding a supporting board on a front surface of a semiconductor substrate to cover a pad electrode formed on the semiconductor substrate with a silicon oxide film interposed therebetween, a process for forming a via hole from a back surface of the semiconductor substrate to a surface of the pad electrode, a process for forming a first opening in the semiconductor substrate to a position where the silicon oxide film is not exposed with using etching gas containing SF6 and O2 at least, and a process for forming a second opening in the semiconductor substrate to a position where the silicon oxide film is exposed with using etching gas containing C4F8 and SF6 at least.

摘要翻译： 本发明提供一种用于防止开口变形而不降低生产率的蚀刻方法。 本发明具有将半导体衬底的前表面上的支撑板接合以覆盖形成在半导体衬底上的衬垫电极的工艺，其中介于其间的氧化硅膜，用于从半导体的背面形成通孔的工艺 衬底到焊盘电极的表面，用于在半导体衬底中形成第一开口到使用含有SF 6和O 3的蚀刻气体不暴露氧化硅膜的位置的工艺， 2＆gt;中所述的方法，以及在所述半导体衬底中形成第二开口的工艺，其中所述氧化硅膜暴露于使用含有C 4 C 8的蚀刻气体的位置处， / SUB>和SF <6>至少。

公开(公告)号：US20050189637A1

公开(公告)日：2005-09-01

申请号：US11055707

申请日：2005-02-11

申请人： Yoshio Okayama ,  Akira Suzuki ,  Koujiro Kameyama ,  Mitsuo Umemoto ,  Kenji Takahashi ,  Hiroshi Terao ,  Masataka Hoshino

发明人： Yoshio Okayama ,  Akira Suzuki ,  Koujiro Kameyama ,  Mitsuo Umemoto ,  Kenji Takahashi ,  Hiroshi Terao ,  Masataka Hoshino

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495

CPC分类号： H01L24/12 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05599

摘要： A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.

摘要翻译： 提供了可靠性提高的半导体器件及其制造方法。 本发明的半导体器件包括半导体衬底，通过由氧化硅，氮化硅等形成的绝缘层在半导体衬底上形成的焊盘电极，接合到半导体衬底的顶表面以覆盖衬垫的支撑板 电极和形成在半导体衬底中并从半导体衬底的背表面延伸到焊盘电极的通孔，其中靠近焊盘电极的部分处的通孔的孔径大于通孔的孔径 靠近半导体衬底的背表面的部分。

公开(公告)号：US09165898B2

公开(公告)日：2015-10-20

申请号：US12346667

申请日：2008-12-30

申请人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

发明人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L24/11 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.

摘要翻译： 提供了可靠性提高的半导体器件及其制造方法。 本发明的半导体器件包括通过第一绝缘层形成在半导体衬底上的焊盘电极和形成在半导体衬底中并从半导体衬底的背表面延伸到焊盘电极的通孔，其中通孔包括 第一开口部，其靠近焊盘电极的部分的直径大于靠近半导体基板的背面的部分的直径;以及第二开口，形成在第一绝缘层中并与第一开口连续， 其中靠近焊盘电极的部分的直径小于靠近半导体衬底的前表面的部分的直径。

公开(公告)号：US08237258B2

公开(公告)日：2012-08-07

申请号：US12394721

申请日：2009-02-27

申请人： Kouichi Saitou ,  Yoshio Okayama ,  Yasuyuki Yanase ,  Takahiro Fujii

发明人： Kouichi Saitou ,  Yoshio Okayama ,  Yasuyuki Yanase ,  Takahiro Fujii

IPC分类号： H01L23/485

CPC分类号： H01L23/5389 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511

摘要： A semiconductor module includes a device mounting board and a semiconductor device mounted on the device mounting board. The device mounting board includes an insulating resin layer, a wiring layer provided on one main surface of the insulating resin layer, and bump electrodes, electrically connected to the wiring layer, which are protruded from the wiring layer toward the insulating resin layer. The semiconductor device has device electrodes which are disposed counter to a semiconductor substrate and the bump electrodes, respectively. The surface of a metallic layer provided on the device electrode lies on the same plane as the surface of a protective layer.

摘要翻译： 半导体模块包括装置安装板和安装在装置安装板上的半导体装置。 装置安装板包括绝缘树脂层，设置在绝缘树脂层的一个主表面上的布线层和从布线层向绝缘树脂层突出的与布线层电连接的凸起电极。 半导体器件具有分别与半导体衬底和凸起电极相对设置的器件电极。 设置在器件电极上的金属层的表面位于与保护层的表面相同的平面上。

公开(公告)号：US08129219B2

公开(公告)日：2012-03-06

申请号：US11863647

申请日：2007-09-28

申请人： Yoshio Okayama

发明人： Yoshio Okayama

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/16 ,  H01L2224/83101 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18301 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81

摘要： In a semiconductor module where a metal sheet, an insulating layer and a circuit element are stacked in a manner that the insulating layer is penetrated with a bump structure, the connection reliability of the bump structure and the circuit element is enhanced. A semiconductor wafer is prepared where a semiconductor substrate having electrodes and protective film on the surface are arranged in a matrix shape. On the surface of the semiconductor substrate, an insulating layer is held between the substrate and a copper sheet, integrally formed with bumps, having grooves in the vicinity of the bumps. The semiconductor substrate, the insulating layer and the copper sheet are press-bonded by a press machine into a single block. The bump penetrates the insulating layer, and the bump and the electrode are electrically connected together. An extra part of the insulating layer pushed out by the bump flows into the groove.

摘要翻译： 在金属片，绝缘层和电路元件以绝缘层穿透凸块结构的方式层叠的半导体模块中，凸块结构和电路元件的连接可靠性提高。 准备半导体晶片，其中具有电极的半导体衬底和表面上的保护膜被排列成矩阵形状。 在半导体基板的表面上，绝缘层保持在基板和铜片之间，与凸块一体形成，在凸块附近具有凹槽。 半导体衬底，绝缘层和铜片通过压制机压接成单个块。 凸块穿透绝缘层，凸块和电极电连接在一起。 由凸块推出的绝缘层的额外部分流入凹槽。

公开(公告)号：US07485967B2

公开(公告)日：2009-02-03

申请号：US11362503

申请日：2006-02-27

申请人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

发明人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.

摘要翻译： 提供了可靠性提高的半导体器件及其制造方法。 本发明的半导体器件包括通过第一绝缘层形成在半导体衬底上的焊盘电极和形成在半导体衬底中并从半导体衬底的背表面延伸到焊盘电极的通孔，其中通孔包括 第一开口部，其靠近焊盘电极的部分的直径大于靠近半导体基板的背面的部分的直径;以及第二开口，形成在第一绝缘层中并与第一开口连续， 其中靠近焊盘电极的部分的直径小于靠近半导体衬底的前表面的部分的直径。

公开(公告)号：US06831015B1

公开(公告)日：2004-12-14

申请号：US08921250

申请日：1997-08-29

申请人： Yasunori Inoue ,  Yoshio Okayama

发明人： Yasunori Inoue ,  Yoshio Okayama

IPC分类号： H01L21302

CPC分类号： H01L21/31155 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

摘要： A fabrication method of a semiconductor device improved in the polishing rate of an insulation film and less likely to generate a defect during polishing is obtained. In this fabrication of a semiconductor device, impurities are introduced into a first insulation film, and then planarization is effected by polishing the surface of the first insulation film. Thus, the polishing rate of the portion of the first insulation film in which impurities are introduced is improved. Also a defect is not easily generated therein.

摘要翻译： 获得半导体器件的制造方法，其改善了绝缘膜的抛光速率并且在抛光期间不太可能产生缺陷。 在这种半导体器件的制造中，将杂质引入第一绝缘膜中，然后通过抛光第一绝缘膜的表面进行平坦化。 因此，导入杂质的第一绝缘膜的部分的研磨速度提高。 另外也不容易产生缺陷。