公开(公告)号：US08338946B2

公开(公告)日：2012-12-25

申请号：US12961171

申请日：2010-12-06

申请人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

发明人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/94 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

摘要翻译： 在半导体模块中的半导体衬底的安装表面（特别是其外周）上形成用于半导体器件的电极。 为了确保电极之间的大间隙，在电极上形成绝缘层。 还形成有穿过绝缘层并连接到电极的多个凸块，以及与凸块一体形成的重新布线图案。 重新布线图案包括凸起区域和与凸起区域相邻延伸的布线区域。 绝缘层形成为具有在凸起之间的间隔中的凹的上表面，并且重新布线图案的布线区域形成为适合该上表面。 重布线图案的布线区域相对于重新布线图案的凸起区域形成为朝向半导体基板压下。

公开(公告)号：US08309864B2

公开(公告)日：2012-11-13

申请号：US12364084

申请日：2009-02-02

申请人： Hajime Kobayashi ,  Yasuyuki Yanase ,  Tetsuya Yamamoto ,  Yoshio Okayama

发明人： Hajime Kobayashi ,  Yasuyuki Yanase ,  Tetsuya Yamamoto ,  Yoshio Okayama

IPC分类号： H05K1/11

CPC分类号： H01L23/49816 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012

摘要： A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode.

摘要翻译： 装置安装板包括：绝缘树脂层; 布置在所述绝缘树脂层的一个主表面上的布线层; 以及与布线层电连接并且在绝缘树脂层的与布线层一侧突出的突起电极。 凸起电极的侧表面在包括突起电极的中心轴的横截面中观察时朝向突起电极的中心轴线弯曲，并且侧表面的曲率半径从布线层端部连续变化到 凸起电极的头端。

公开(公告)号：US20120160903A1

公开(公告)日：2012-06-28

申请号：US13392835

申请日：2011-05-31

申请人： Kouichi Saitou ,  Yoshio Okayama

发明人： Kouichi Saitou ,  Yoshio Okayama

IPC分类号： B23K31/02

CPC分类号： B23K20/023 ,  B23K2103/12 ,  H01L24/83 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83895

摘要： The present invention provides a method of joining a metal that can join coppers at a relatively low temperature by a simple technique while maintaining connection reliability.The space between a first coating portion (14) (a copper oxide) coating a first base portion (12) (copper) and a second coating portion (24) (a copper oxide) coating a second base portion (22) (copper) is filled with a solution (30) in which the copper oxide of the first coating portion (14) and the copper oxide of the second coating portion (24) are to be eluted. As a result, the copper oxides forming the first coating portion (14) and the second coating portion (24) are eluted in the solution (30). To increase the pressure of the solution (30), pressure is applied to a first to-be-joined portion (10) and a second to-be-joined portion (20) with a pressing machine. During the pressure application, heating is performed at a relatively low temperature of 200 to 300° C., to remove the components other than the copper in the solution (30) and precipitate the copper. The first base portion (12) and the second base portion (22) are joined to each other by the precipitated copper.

摘要翻译： 本发明提供了一种在保持连接可靠性的情况下，通过简单的技术连接可以在较低温度下连接铜的金属的方法。 涂覆有第一基部（12）（铜）的第一涂覆部分（氧化铜）和涂覆有第二基底部分（22）（铜）的第二涂覆部分（二氧化铜））之间的空间， 填充有第一涂布部分（14）的氧化铜和第二涂布部分（24）的氧化铜被洗脱的溶液（30）。 结果，形成第一涂布部分（14）和第二涂覆部分（24）的氧化铜在溶液（30）中被洗脱。 为了增加溶液（30）的压力，用压制机将压力施加到第一待接合部分（10）和第二待接合部分（20）。 在压力施加期间，在200〜300℃的较低温度下进行加热，除去溶液（30）中的铜以外的成分，使铜沉淀。 第一基部（12）和第二基部（22）通过沉淀的铜彼此连接。

公开(公告)号：US20080217769A1

公开(公告)日：2008-09-11

申请号：US12022865

申请日：2008-01-30

申请人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

发明人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/94 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area.The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

摘要翻译： 在半导体模块中的半导体衬底的安装表面（特别是其外周）上形成用于半导体器件的电极。 为了确保电极之间的大间隙，在电极上形成绝缘层。 还形成有穿过绝缘层并连接到电极的多个凸块，以及与凸块一体形成的重新布线图案。 重新布线图案包括凸起区域和与凸起区域相邻延伸的布线区域。 绝缘层形成为具有在凸起之间的间隔中的凹的上表面，并且重新布线图案的布线区域形成为适合该上表面。 重布线图案的布线区域相对于重新布线图案的凸起区域形成为朝向半导体基板压下。

公开(公告)号：US07172962B2

公开(公告)日：2007-02-06

申请号：US10724111

申请日：2003-12-01

申请人： Yoshio Okayama ,  Hayato Nakashima ,  Yoshinari Ichihashi

发明人： Yoshio Okayama ,  Hayato Nakashima ,  Yoshinari Ichihashi

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/7688 ,  H01L21/7684

摘要： On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.

摘要翻译： 在衬底上依次形成第一互连203，扩散阻挡膜205和第二绝缘膜207，然后在第二绝缘膜207的上表面上形成牺牲膜213。 接下来，形成通孔211和互连沟槽217，然后在牺牲膜213上形成阻挡金属膜219和铜膜221。 用于去除外部铜膜221和阻挡金属膜219的CMP以两步法进行，即， 即，在阻挡金属膜219的表面上停止抛光的第一次抛光和抛光剩余的阻挡金属膜219和锥形牺牲膜213的第二次抛光。

公开(公告)号：US20060120010A1

公开(公告)日：2006-06-08

申请号：US11287484

申请日：2005-11-28

申请人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

发明人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

IPC分类号： H01T23/00

CPC分类号： H01L21/6833 ,  H01L21/6831

摘要： The invention provides an electrostatically chucking technology capable of chucking a workpiece formed of an insulator or a workpiece attached with an object to be processed such as a semiconductor wafer on a stage. A layered body attached with a glass substrate for supporting a semiconductor substrate having an electronic device on its surface is prepared, and a conductive film is attached thereto. Then, the layered body is set on a surface of a stage set in a vacuum chamber such as a dry-etching apparatus. After then, a voltage is applied to an internal electrode to generate positive and negative electric charges on the surfaces of the conductive film and the stage, and the layered body is chucked with static electricity generated therebetween. Then, the layered body chucked on the stage is processed by etching, CVD, or PVD.

公开(公告)号：US08362611B2

公开(公告)日：2013-01-29

申请号：US12679595

申请日：2008-09-25

申请人： Yasuyuki Yanase ,  Yoshio Okayama ,  Ryosuke Usui

发明人： Yasuyuki Yanase ,  Yoshio Okayama ,  Ryosuke Usui

IPC分类号： H01L23/488

CPC分类号： H01L24/11 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2924/00

摘要： A semiconductor module is of a structure such that a wiring layer, an insulating resin layer and a semiconductor device are stacked in this order by bonding them together with compression. In the wiring layer, bump electrodes each having a base and a tip portion are provided in positions corresponding respectively to device electrodes of the semiconductor device. The bump electrodes penetrate the insulating resin layer and are electrically coupled to the corresponding device electrodes.

摘要翻译： 半导体模块具有这样的结构，使得布线层，绝缘树脂层和半导体器件通过将它们压缩在一起而依次堆叠。 在布线层中，各自具有基底和尖端部分的凸起电极设置在分别对应于半导体器件的器件电极的位置。 凸块电极穿透绝缘树脂层并电耦合到相应的器件电极。

公开(公告)号：US08274148B2

公开(公告)日：2012-09-25

申请号：US12727565

申请日：2010-03-19

申请人： Yasuyuki Yanase ,  Atsunobu Suzuki ,  Yoshio Okayama

发明人： Yasuyuki Yanase ,  Atsunobu Suzuki ,  Yoshio Okayama

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/94 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.

摘要翻译： 第一电路元件和第二元件安装成其电极形成表面面向布线层。 与一个面上的布线层一体形成的第一凸块电极基本上贯穿第一绝缘树脂层。 覆盖第一电路元件的元件电极的镀金层和设置在第一凸块电极顶部的镀金层通过Au-Au键合而接合在一起。 与一个面上的布线层一体形成的第二凸块电极基本上贯穿第一绝缘树脂层和第二绝缘树脂层。 覆盖第二电路元件的元件电极的镀金层和设置在第二凸块电极顶部的金镀层通过Au-Au键合而接合在一起。

公开(公告)号：US07915737B2

公开(公告)日：2011-03-29

申请号：US11957030

申请日：2007-12-14

申请人： Mayumi Nakasato ,  Yoshio Okayama ,  Ryosuke Usui

发明人： Mayumi Nakasato ,  Yoshio Okayama ,  Ryosuke Usui

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A manufacturing technology is provided capable of improving the reliability of a semiconductor module having a via contact connected to an electrode part of a semiconductor component. The semiconductor module includes: a semiconductor component provided with an electrode part on a mounting surface; an insulating layer provided on the mounting surface of the semiconductor component; a wiring layer formed on the insulating layer; a first conductor part which is embedded in the insulating layer and which is in contact with the electrode part; and a second conductor part which is formed in an aperture provided in the insulating layer above the first conductor part and which electrically connects the first conductor part and the wiring layer.

摘要翻译： 提供一种制造技术，其能够提高具有连接到半导体部件的电极部分的通孔接触的半导体模块的可靠性。 半导体模块包括：在安装表面上设置有电极部分的半导体部件; 设置在所述半导体部件的安装面上的绝缘层; 形成在所述绝缘层上的布线层; 第一导体部，其嵌入绝缘层中并与电极部接触; 以及第二导体部，其形成在设置在所述第一导体部分上方的所述绝缘层中的孔中，并且将所述第一导体部和所述布线层电连接。

公开(公告)号：US20100276800A1

公开(公告)日：2010-11-04

申请号：US12727565

申请日：2010-03-19

申请人： Yasuyuki YANASE ,  Atsunobu Suzuki ,  Yoshio Okayama

发明人： Yasuyuki YANASE ,  Atsunobu Suzuki ,  Yoshio Okayama

IPC分类号： H01L23/538

CPC分类号： H01L24/94 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.

摘要翻译： 第一电路元件和第二元件安装成其电极形成表面面向布线层。 与一个面上的布线层一体形成的第一凸块电极基本上贯穿第一绝缘树脂层。 覆盖第一电路元件的元件电极的镀金层和设置在第一凸块电极顶部的镀金层通过Au-Au键合而接合在一起。 与一个面上的布线层一体形成的第二凸块电极基本上贯穿第一绝缘树脂层和第二绝缘树脂层。 覆盖第二电路元件的元件电极的镀金层和设置在第二凸块电极顶部的金镀层通过Au-Au键合而接合在一起。