公开(公告)号：US09165898B2

公开(公告)日：2015-10-20

申请号：US12346667

申请日：2008-12-30

申请人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

发明人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L24/11 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.

摘要翻译： 提供了可靠性提高的半导体器件及其制造方法。 本发明的半导体器件包括通过第一绝缘层形成在半导体衬底上的焊盘电极和形成在半导体衬底中并从半导体衬底的背表面延伸到焊盘电极的通孔，其中通孔包括 第一开口部，其靠近焊盘电极的部分的直径大于靠近半导体基板的背面的部分的直径;以及第二开口，形成在第一绝缘层中并与第一开口连续， 其中靠近焊盘电极的部分的直径小于靠近半导体衬底的前表面的部分的直径。

公开(公告)号：US08154129B2

公开(公告)日：2012-04-10

申请号：US12307228

申请日：2008-04-04

申请人： Kikuo Okada ,  Kojiro Kameyama ,  Takahiro Oikawa

发明人： Kikuo Okada ,  Kojiro Kameyama ,  Takahiro Oikawa

IPC分类号： H01L23/492

CPC分类号： H01L23/49562 ,  H01L23/4952 ,  H01L23/49524 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7809 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/371 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099

摘要： In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.

摘要翻译： 在功率MOS晶体管中，例如，源极电极形成为与形成在前表面上的多个源极区域共同连接。 因此，电流密度基于源电极的面内电阻而变化，由此提供增加连接源极和引线的导线数量的必要性。 在本发明中，电极结构包括通过电解电镀法形成在焊盘电极10a上的镀铜层10e，以及形成为覆盖铜镀层的上表面和侧表面的镀镍层10f和镀金层 层10e通过化学镀方法。

公开(公告)号：US07485967B2

公开(公告)日：2009-02-03

申请号：US11362503

申请日：2006-02-27

申请人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

发明人： Kojiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.

摘要翻译： 提供了可靠性提高的半导体器件及其制造方法。 本发明的半导体器件包括通过第一绝缘层形成在半导体衬底上的焊盘电极和形成在半导体衬底中并从半导体衬底的背表面延伸到焊盘电极的通孔，其中通孔包括 第一开口部，其靠近焊盘电极的部分的直径大于靠近半导体基板的背面的部分的直径;以及第二开口，形成在第一绝缘层中并与第一开口连续， 其中靠近焊盘电极的部分的直径小于靠近半导体衬底的前表面的部分的直径。

公开(公告)号：US20080132038A1

公开(公告)日：2008-06-05

申请号：US11969065

申请日：2008-01-03

申请人： Kojiro Kameyama ,  Akira Suzuki ,  Mitsuo Umemoto

发明人： Kojiro Kameyama ,  Akira Suzuki ,  Mitsuo Umemoto

IPC分类号： H01L21/304 ,  H01L21/4763

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/351 ,  Y10S438/978 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.

摘要翻译： 本发明涉及一种具有穿透电极的半导体器件及其制造方法，其中提高了半导体器件的可靠性和产量。 蚀刻半导体衬底以从半导体衬底的背表面到焊盘电极形成通孔。 该蚀刻在蚀刻条件下进行，使得其底部的通孔的开口直径大于焊盘电极的宽度。 接下来，在包括在通孔16中的半导体衬底的背面上形成第二绝缘膜，使通孔底部的焊盘电极露出。 接下来，形成贯通电极和布线层，与在通孔16的底部露出的焊盘电极电连接。 此外，形成保护层和导电端子。 最后，通过切割在半导体管芯中切割和分离半导体衬底。

公开(公告)号：US20060108691A1

公开(公告)日：2006-05-25

申请号：US11260682

申请日：2005-10-28

申请人： Kojiro Kameyama ,  Akira Suzuki ,  Mitsuo Umemoto

发明人： Kojiro Kameyama ,  Akira Suzuki ,  Mitsuo Umemoto

IPC分类号： H01L23/52

CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/02 ,  H01L24/10 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/04941

摘要： The first pad electrode layer is disposed on the surface of the semiconductor substrate with the first insulating film between them. Then, the second insulating film with the first via hole partially exposing the first pad electrode layer is formed over the first pad electrode layer. The plug is formed in the first via hole in the next process. The second pad electrode layer connected to the plug is disposed on the second insulating film. Next, the second via hole reaching to the first pad electrode layer from the backside of the semiconductor substrate is formed. The penetrating electrode and the second wiring layer connected to the first pad electrode layer at the bottom part of the second via hole are disposed. Furthermore, the protecting layer and the conductive terminal are formed. Finally, the semiconductor substrate is diced into the semiconductor chips.

摘要翻译： 第一焊盘电极层设置在半导体衬底的表面上，其间具有第一绝缘膜。 然后，在第一焊盘电极层上形成具有部分地露出第一焊盘电极层的第一通孔的第二绝缘膜。 在下一个过程中，插头形成在第一通孔中。 连接到插头的第二焊盘电极层设置在第二绝缘膜上。 接下来，形成从半导体基板的背面到达第一焊盘电极层的第二通孔。 设置在第二通孔的底部连接到第一焊盘电极层的穿透电极和第二布线层。 此外，形成保护层和导电端子。 最后，将半导体衬底切成半导体芯片。

公开(公告)号：US20060071342A1

公开(公告)日：2006-04-06

申请号：US11236881

申请日：2005-09-28

申请人： Mitsuo Umemoto ,  Kojiro Kameyama ,  Akira Suzuki

发明人： Mitsuo Umemoto ,  Kojiro Kameyama ,  Akira Suzuki

IPC分类号： H01L23/48

CPC分类号： H01L27/1462 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/564 ,  H01L27/14636 ,  H01L2924/0002 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.

摘要翻译： 本发明旨在通过防止保护膜和绝缘膜剥离来提高具有穿透电极的半导体器件的可靠性。 在半导体器件的角部形成有用于防止绝缘膜和保护层剥离的防剥层。 当形成在除了角部之外的半导体器件的空置空间中时，例如在球形导电端子之间，防剥层可以增加其防剥离效果。 在半导体器件的横截面中，在半导体衬底的背面上的绝缘膜上形成防剥层，并且形成覆盖绝缘膜的防焊层等形成的防剥离层 层。 当通过电解电镀法形成时，防剥层具有阻挡种子层和形成在其上的铜层的叠层结构。

公开(公告)号：US07659576B2

公开(公告)日：2010-02-09

申请号：US11933897

申请日：2007-11-01

申请人： Kikuo Okada ,  Kojiro Kameyama

发明人： Kikuo Okada ,  Kojiro Kameyama

IPC分类号： H01L29/78

CPC分类号： H01L29/7395 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66333

摘要： A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

摘要翻译： 穿通型IGBT通常具有厚的p ++型集电极层。 因此，当IGBT用作用于驱动电动机负载的逆变器电路中的开关元件时，FWD需要外部附接到IGBT，因此工艺和部件的数量增加。 在本发明中，形成贯通收集层并到达缓冲层的沟槽。 集电极也形成在沟槽中。 利用这种结构，在发射电极和集电极之间形成电流通路，而不通过集电极层，起到FWD的作用。

公开(公告)号：US07382037B2

公开(公告)日：2008-06-03

申请号：US11236881

申请日：2005-09-28

申请人： Mitsuo Umemoto ,  Kojiro Kameyama ,  Akira Suzuki

发明人： Mitsuo Umemoto ,  Kojiro Kameyama ,  Akira Suzuki

IPC分类号： H01L23/544

CPC分类号： H01L27/1462 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/564 ,  H01L27/14636 ,  H01L2924/0002 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.

摘要翻译： 本发明旨在通过防止保护膜和绝缘膜剥离来提高具有穿透电极的半导体器件的可靠性。 在半导体器件的角部形成有用于防止绝缘膜和保护层剥离的防剥层。 当形成在除了角部之外的半导体器件的空置空间中时，例如在球形导电端子之间，防剥层可以增加其防剥离效果。 在半导体器件的横截面中，在半导体衬底的背面上的绝缘膜上形成防剥层，并且形成覆盖绝缘膜的防焊层等形成的防剥离层 层。 当通过电解电镀法形成时，防剥层具有阻挡种子层和形成在其上的铜层的叠层结构。

公开(公告)号：US07339273B2

公开(公告)日：2008-03-04

申请号：US11257390

申请日：2005-10-25

申请人： Kojiro Kameyama ,  Akira Suzuki ,  Mitsuo Umemoto

发明人： Kojiro Kameyama ,  Akira Suzuki ,  Mitsuo Umemoto

IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/351 ,  Y10S438/978 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.

摘要翻译： 本发明涉及一种具有穿透电极的半导体器件及其制造方法，其中提高了半导体器件的可靠性和产量。 蚀刻半导体衬底以从半导体衬底的背表面到焊盘电极形成通孔。 该蚀刻在蚀刻条件下进行，使得其底部的通孔的开口直径大于焊盘电极的宽度。 接下来，在包括在通孔16中的半导体衬底的背面上形成第二绝缘膜，使通孔底部的焊盘电极露出。 接下来，形成贯通电极和布线层，与在通孔16的底部露出的焊盘电极电连接。 此外，形成保护层和导电端子。 最后，通过切割在半导体管芯中切割和分离半导体衬底。

公开(公告)号：US20070254471A1

公开(公告)日：2007-11-01

申请号：US11822122

申请日：2007-07-02

申请人： Kojiro Kameyama ,  Akira Suzuki

发明人： Kojiro Kameyama ,  Akira Suzuki

IPC分类号： H01L21/4763

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A result of formation of an opening in a semiconductor substrate can be judged without cutting a semiconductor wafer and observing a cross-section of the cut wafer. A semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an opening formed in the semiconductor substrate to expose the pad electrode, a wiring layer connected with the pad electrode through the opening and a monitoring opening formed in a scribe line to monitor a result of the formation of the opening.