公开(公告)号：US20190393176A1

公开(公告)日：2019-12-26

申请号：US16013237

申请日：2018-06-20

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Gambee ,  Nhi Doan ,  Chandra S. Tiwari ,  Owen R. Fay ,  Ying Chen

IPC: H01L23/00 ,  H01L21/027 ,  H01L21/56

Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.

公开(公告)号：US20190189507A1

公开(公告)日：2019-06-20

申请号：US15841660

申请日：2017-12-14

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Gambee

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76865 ,  H01L21/76873 ,  H01L23/53238 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2924/3011

Abstract: A method of forming conductive traces comprises forming a seed material over a surface of a substrate, forming a patterned mask material over the seed material to define trenches leaving portions of the seed material within the trenches exposed, and depositing a conductive material over the exposed seed material in the trenches to form conductive traces. At least a portion of the patterned mask material is removed, a barrier formed over side surfaces and upper surfaces of the conductive traces, and exposed portions of the seed material are removed. Conductive traces and structures incorporating conductive traces are also disclosed.

公开(公告)号：US20190051623A1

公开(公告)日：2019-02-14

申请号：US15982129

申请日：2018-05-17

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US20160172242A1

公开(公告)日：2016-06-16

申请号：US15050858

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US09318438B2

公开(公告)日：2016-04-19

申请号：US14679845

申请日：2015-04-06

Applicant: Micron Technology, Inc.

Inventor： Mark A. Bossler ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Randall S. Parker

IPC: H01L23/532 ,  H01L23/538 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L23/53238 ,  H01L21/02068 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for selectively removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract translation: 一种用于从衬底选择性地去除材料的方法，而不损坏铜填充通孔并且至少部分地延伸通过衬底。 该方法包括氧化包括基底和至少一个铜特征的半导体结构，并且使用包含SF 6的蚀刻剂去除一部分基底，而不在至少一个铜特征上形成硫化铜。 还公开了另外的方法，以及由这些方法制备的半导体结构。

公开(公告)号：US09299663B2

公开(公告)日：2016-03-29

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/04 ,  H01L23/544 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。

公开(公告)号：US20150333014A1

公开(公告)日：2015-11-19

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。

公开(公告)号：US20140167259A1

公开(公告)日：2014-06-19

申请号：US14186869

申请日：2014-02-21

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Luke G. England ,  Christopher J. Gambee

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/0274 ,  H01L21/311 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2224/11

Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Abstract translation: 制造用于半导体晶片的互连结构的方法包括形成与导电元件的全柱直径上的有源表面上的接合焊盘接触的导电元件，随后将包含光致抗蚀剂的可光限定材料施加到有源表面上并在导电元件上 。 聚酰亚胺材料被选择性地曝光和显影以除去覆盖至少导电元件顶部的可光限定材料。 还公开了半导体管芯和半导体管芯组件。

公开(公告)号：US10896886B2

公开(公告)日：2021-01-19

申请号：US16276533

申请日：2019-02-14

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US10403618B2

公开(公告)日：2019-09-03

申请号：US15711937

申请日：2017-09-21

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Tony M. Lindenberg ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Kurt J. Bossart

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/02

Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.