公开(公告)号：US10950564B2

公开(公告)日：2021-03-16

申请号：US16414440

申请日：2019-05-16

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US10937749B2

公开(公告)日：2021-03-02

申请号：US16540444

申请日：2019-08-14

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L25/00

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

公开(公告)号：US20210050327A1

公开(公告)日：2021-02-18

申请号：US17087867

申请日：2020-11-03

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.

公开(公告)号：US20190273058A1

公开(公告)日：2019-09-05

申请号：US16414440

申请日：2019-05-16

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US10381301B2

公开(公告)日：2019-08-13

申请号：US15428124

申请日：2017-02-08

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683

Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.

公开(公告)号：US20180323160A1

公开(公告)日：2018-11-08

申请号：US16039652

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

公开(公告)号：US10121849B2

公开(公告)日：2018-11-06

申请号：US14941665

申请日：2015-11-16

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC: H01L49/02 ,  H01L21/304 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L29/92 ,  C23C14/16 ,  C23C16/06 ,  C23C16/40 ,  C23C16/34 ,  C23C14/06 ,  C23C14/10 ,  C23C14/08 ,  H01L21/3065 ,  H01L23/48

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.

公开(公告)号：US20170365580A1

公开(公告)日：2017-12-21

申请号：US15676350

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/81

Abstract: A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die ant the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.

公开(公告)号：US09761540B2

公开(公告)日：2017-09-12

申请号：US14927491

申请日：2015-10-30

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/373 ,  H01L23/16 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor device that includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is electrically connected to the chip. A molding compound covers and encapsulates the chip. A first stress-relief feature is embedded in the molding compound within a peripheral area adjacent to the chip mounting area. A second stress-relief feature is embedded in the molding compound within the chip mounting area. The first stress-relief feature is composed of a first material. The second stress-relief feature is composed of a second material that is different from the first material.

公开(公告)号：US09704790B1

公开(公告)日：2017-07-11

申请号：US15069911

申请日：2016-03-14

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC: H01L21/44 ,  H01L23/12 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/50 ,  H01L21/78 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2021/60255 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side, opposite to the first side. The RDL interposer comprises a first passivation layer, at least one dielectric layer on the first passivation layer, a metal layer in the at least one dielectric layer, a second passivation layer on the at least one dielectric layer, and a plurality of ball pads in the first passivation layer. At least one semiconductor die is mounted on the first side of the RDL interposer. A solder mask covers a lower surface of the first passivation layer and exposes the plurality of ball pads through a plurality of openings in the solder mask. An under-bump mettalization (UBM) layer is disposed at a bottom of each of the plurality of openings. A solder bump or solder ball is disposed on the UBM layer in each of the plurality of openings.