公开(公告)号：US20150357257A1

公开(公告)日：2015-12-10

申请号：US14828517

申请日：2015-08-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L23/34 ,  H01L23/522 ,  H01L23/50 ,  H01L27/06

CPC classification number: H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K19/096 ,  H03K19/1774 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the second clock distribution structure is connected to the first clock distribution structure with a plurality of through layer vias, and where the second transistors are aligned to the first transistors with less than 100 nm alignment error.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，覆盖第一层互连层的第二晶体管，其中第一层包括第一时钟分配结构，其中第二层包括第二时钟分配结构，其中第二时钟分配结构连接到第一层 具有多个贯通层通孔的时钟分配结构，并且其中第二晶体管与具有小于100nm对准误差的第一晶体管对准。

公开(公告)号：US20150348945A1

公开(公告)日：2015-12-03

申请号：US14821683

申请日：2015-08-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman ,  Israel Beinglass

IPC: H01L25/065 ,  H01L23/532 ,  H01L29/45 ,  H01L27/088 ,  H01L27/06 ,  H01L23/544 ,  H01L23/522

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 互连第一晶体管并覆盖第一层的第一互连层; 以及包括第二晶体管的第二层，其中所述第二层厚度小于2微米且大于5nm，其中所述第二层覆盖所述第一互连层，并且其中所述第二层包括通过蚀刻步骤形成的管芯线。

公开(公告)号：US20150205903A1

公开(公告)日：2015-07-23

申请号：US14672202

申请日：2015-03-29

Applicant: MONOLITHIC 3D INC.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a first strata and a second strata; then performing a first placement of the first strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of the second strata based on the first placement, where the partitioning includes a partition between logic and memory, and where the logic includes at least one decoder representation for the memory.

Abstract translation: 一种设计3D集成电路的方法，所述方法包括：对至少第一层和第二层进行划分; 然后使用由计算机执行的2D放样器来执行第一层的第一放置，其中2D贴片是当前在工业中用于二维器件的计算机辅助设计（CAD）工具; 以及基于所述第一布置执行所述第二层的第二布置，其中所述分区包括逻辑和存储器之间的分区，以及所述逻辑包括用于所述存储器的至少一个解码器表示。

公开(公告)号：US09021414B1

公开(公告)日：2015-04-28

申请号：US13862537

申请日：2013-04-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing placement using a 2D placer, performing placement for at least a first strata and a second strata, and then performing routing and completing the physical design of said 3D Integrated Circuit.

Abstract translation: 一种设计3D集成电路的方法，所述方法包括：使用2D放置器执行放置，执行至少第一层和第二层的放置，然后执行路由并完成所述3D集成电路的物理设计。

公开(公告)号：US08993385B1

公开(公告)日：2015-03-31

申请号：US14491489

申请日：2014-09-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L21/84 ,  H01L23/482 ,  H01L21/302 ,  H01L21/268 ,  H01L21/8238 ,  H01L21/8232

CPC classification number: H01L23/4827 ,  H01L21/268 ,  H01L21/302 ,  H01L21/76232 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8232 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/481 ,  H01L23/49827 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/1203 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/01066 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A method to construct a semiconductor device, the method including: forming a first layer including mono-crystallized semiconductor and first logic circuits; forming a second layer including a mono-crystallized semiconductor layer, the second layer overlying the first logic circuits; forming transistors on the second layer; forming connection paths from the second transistors to the first transistors, where the connection paths include a through layer via of less than 200 nm diameter; and connecting the first logic circuits to an external device using input/output (I/O) circuits, the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.

Abstract translation: 一种构造半导体器件的方法，所述方法包括：形成包括单结晶半导体的第一层和第一逻辑电路; 形成包括单结晶半导体层的第二层，所述第二层覆盖所述第一逻辑电路; 在第二层上形成晶体管; 形成从第二晶体管到第一晶体管的连接路径，其中连接路径包括直径小于200nm的贯穿层通孔; 并且使用输入/输出（I / O）电路将第一逻辑电路连接到外部设备，所述输入/输出（I / O）电路构造在第二单结晶半导体层上。

公开(公告)号：US11720736B2

公开(公告)日：2023-08-08

申请号：US18111567

申请日：2023-02-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing placement data of the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

公开(公告)号：US11574109B1

公开(公告)日：2023-02-07

申请号：US17953211

申请日：2022-09-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes logic and the second level includes memory; and then obtaining a first placement of at least portion of the second level, where the first placement includes placement of a first memory array, where the Circuit includes a plurality of connections between the first level and the second level; and performing a second placement, where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array, where the performing a second placement includes using a placer executed by a computer, where the placer is a part of a Computer Aided Design tool, and where the logic includes a first logic circuit configured to read data from the first memory array.

公开(公告)号：US20220222414A1

公开(公告)日：2022-07-14

申请号：US17712850

申请日：2022-04-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least a first and a second level, where the first level includes logic and the second level includes memory; then performing a first placement of the second level using a placer executed by a computer, the placer is a part of a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the first level and the second level; and performing a second placement of the first level based on the first placement, where memory includes a first memory array, the logic includes a first logic circuit configured so as to write data to first memory array. Performing the first placement includes placing the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.

公开(公告)号：US11270055B1

公开(公告)日：2022-03-08

申请号：US17523904

申请日：2021-11-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, where the 3D Integrated Circuit includes a plurality of connections between the logic strata and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit controlling the first memory array, where the first placement includes placement of the first memory array, where the second placement includes placement of the first logic circuit based on the placement of the first memory array.

公开(公告)号：US11121021B2

公开(公告)日：2021-09-14

申请号：US16101489

申请日：2018-08-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/683 ,  G11C8/16 ,  H01L29/792 ,  H01L29/788 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L27/118 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/10 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L23/525 ,  H01L23/48 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/768 ,  H01L21/762 ,  H01L21/74 ,  H01L49/02 ,  H01L27/088 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/544 ,  H01L27/24 ,  H01L45/00

Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.