公开(公告)号：US20240312841A1

公开(公告)日：2024-09-19

申请号：US18602117

申请日：2024-03-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi SAEKI ,  Hidehiko KARASAKI ,  Shogo OKITA ,  Toshiyuki TAKASAKI ,  Akihiro ITOU

IPC: H01L21/78 ,  B23K26/36 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L21/78 ,  B23K26/36 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L2221/68327

Abstract: An element chip manufacturing method disclosed herein includes a preparation process of preparing a substrate having a semiconductor layer, a wiring layer, a plurality of element areas and a dividing area, a resin layer formation process of forming a resin layer covering the wiring layer, an opening formation process of irradiating the wiring layer and the resin layer in the dividing area to form an opening in which the semiconductor layer is exposed in the dividing area, a reflow process of reducing the opening by reflowing the resin layer, and a singulation process of dividing the substrate into a plurality of element chips each including a different one of the element areas, by performing etching of the substrate with plasma along the opening reduced in the reflow process, using the resin layer as a mask.

公开(公告)号：US20230114557A1

公开(公告)日：2023-04-13

申请号：US17937512

申请日：2022-10-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi HARIKAI ,  Shogo OKITA

IPC: H01J37/32

Abstract: A plasma processing apparatus including: a chamber; a plasma generation unit configured to generate a plasma in the chamber; a stage 111 for placing a conveying carrier 10, the stage provided in the chamber; a cover 124 for covering at least part of the conveying carrier placed on the stage; a relative position change unit capable of changing a relative distance between the cover 124 and the stage 111 to a first distance and to a second distance smaller than the first distance; a determination unit configured to determine a placed state of the conveying carrier 10; and a control unit. The determination unit determines the placed state of the conveying carrier while the distance between the cover 124 and the stage 111 is the first distance, and the plasma processing is performed while the distance between the cover 124 and the stage 111 is the second distance.

公开(公告)号：US20220262603A1

公开(公告)日：2022-08-18

申请号：US17737224

申请日：2022-05-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA

IPC: H01J37/32 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/67

Abstract: A dry etching apparatus plasma processes a wafer held by a carrier having a frame and an holding sheet. The carrier is placed on an electrode unit of a stage provided in a chamber. The electrode unit is cooled by a cooling section configured to cool the electrode unit. An upper face of the electrode unit is at least as large as the back side of the carrier. The holding sheet and the frame are cooled effectively by the heat transfer to the stage.

公开(公告)号：US20210057227A1

公开(公告)日：2021-02-25

申请号：US16993466

申请日：2020-08-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro ITOU ,  Atsushi HARIKAI ,  Toshiyuki TAKASAKI ,  Shogo OKITA

IPC: H01L21/3065 ,  H01L21/02

Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.

公开(公告)号：US20200381367A1

公开(公告)日：2020-12-03

申请号：US16872801

申请日：2020-05-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kiyoshi ARITA ,  Shogo OKITA ,  Hidehiko KARASAKI

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/268 ,  H01L21/78 ,  B23K26/57 ,  B23K26/0622 ,  B23K26/18 ,  B23K26/351

Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.

公开(公告)号：US20200381304A1

公开(公告)日：2020-12-03

申请号：US16881165

申请日：2020-05-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi SAEKI ,  Hidehiko KARASAKI ,  Shogo OKITA ,  Atsushi HARIKAI ,  Akihiro ITOU

IPC: H01L21/82 ,  H01L21/56 ,  H01L21/311 ,  H01L21/3065

Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.

公开(公告)号：US20190221479A1

公开(公告)日：2019-07-18

申请号：US16246627

申请日：2019-01-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Atsushi HARIKAI ,  Noriyuki MATSUBARA ,  Hidefumi SAEKI ,  Akihiro ITOU

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/561 ,  H01L21/6836

Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.

公开(公告)号：US20180240678A1

公开(公告)日：2018-08-23

申请号：US15899422

申请日：2018-02-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro ITOU ,  Atsushi HARIKAI ,  Noriyuki MATSUBARA ,  Shogo OKITA

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/687 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/30655 ,  H01J37/00 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32743 ,  H01L21/31138 ,  H01L21/67109 ,  H01L21/6835 ,  H01L21/68735 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78 ,  H01L21/7806 ,  H01L2221/68327

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.

公开(公告)号：US20160064198A1

公开(公告)日：2016-03-03

申请号：US14834992

申请日：2015-08-25

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Shogo OKITA ,  Bunji MIIZUNO ,  Tomohiro OKUMURA

IPC: H01J37/32

CPC classification number: H01J37/32724 ,  H01J37/321 ,  H01J37/32651 ,  H01J37/32697 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/68728 ,  H01L21/68742

Abstract: A plasma processing apparatus that performs plasma processing on a substrate held on a transport carrier including an annular frame and a holding sheet. The apparatus includes a process chamber; a process gas supply unit that supplies process gas to the process chamber; a decompressing mechanism that decompresses the process chamber; a plasma excitation device that generates plasma in the process chamber; a stage in the chamber, on which the transport carrier is loaded; a cooling mechanism for cooling the stage; a cover that partly covers the holding sheet and the frame and that has a window section through which the substrate is partly exposed to plasma; a correction member that presses the frame onto the stage and corrects warpage of the frame; and a movement device that moves the correction member. The correction member is provided separately from the cover to be covered by the cover.

Abstract translation: 一种等离子体处理装置，其在保持在包括环形框架和保持片材的运送载体上的基板上进行等离子体处理。 该装置包括处理室; 处理气体供给单元，其将处理气体供给到处理室; 减压处理室的减压机构; 在处理室中产生等离子体的等离子体激发装置; 运输承运人在该舱的一个阶段; 用于冷却载物台的冷却机构; 部分地覆盖保持片和框架并且具有窗口部分的盖子，衬底部分地暴露于等离子体; 校正构件，其将框架按压到台架上并校正框架的翘曲; 以及使校正构件移动的移动装置。 修正构件与盖子分开设置以被盖覆盖。

公开(公告)号：US20160064188A1

公开(公告)日：2016-03-03

申请号：US14818415

申请日：2015-08-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Hiromi ASAKURA ,  Syouzou WATANABE ,  Noriyuki MATSUBARA ,  Mitsuru HIROSHIMA ,  Toshihiro WADA

IPC: H01J37/32

CPC classification number: H01J37/32715 ,  H01J37/32366 ,  H01J37/32733 ,  H01L21/681

Abstract: A plasma processing apparatus that performs plasma processing to a substrate held on a transport carrier including a frame and a holding sheet that covers an opening of the frame includes: a transport mechanism that transports the transport carrier; a position measuring section that measures a position of the substrate to the frame; a plasma processing section that includes a plasma processing stage on which the transport carrier is loaded and a cover that covers the frame and a part of the holding sheet loaded on the plasma processing stage, and has a window section for exposing a part of the substrate; and a control section that controls the transport mechanism such that the transport carrier is loaded on the plasma processing stage to satisfy a positional relationship between the window section and the substrate based on the position information of the substrate to the frame.

Abstract translation: 对保持在包括框架的运送载体上的基板和覆盖框架的开口的保持片进行等离子体处理的等离子体处理装置包括：运送运送托架的运送机构; 位置测量部，其测量所述基板与所述框架的位置; 等离子体处理部，其包括装载有运送载体的等离子体处理台和覆盖框架的盖和负载在等离子体处理台上的保持片的一部分，并具有用于使基板的一部分露出的窗口部 ; 以及控制部，其控制所述输送机构，使得所述输送载体基于所述基板到所述框架的位置信息而被载载在所述等离子体处理台上以满足所述窗口部和所述基板之间的位置关系。