公开(公告)号：US20080305566A1

公开(公告)日：2008-12-11

申请号：US12197045

申请日：2008-08-22

Applicant: Jiandong Huang ,  Pooran Chandra Joshi ,  Hao Zhang ,  Apostolos T. Voutsas

Inventor： Jiandong Huang ,  Pooran Chandra Joshi ,  Hao Zhang ,  Apostolos T. Voutsas

IPC: H01L21/00

CPC classification number: C23C16/30 ,  C23C16/24 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/0262 ,  H01L21/31608

Abstract: A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.

Abstract translation: 提供了一种用于形成具有中间带隙过渡层的硅（Si）纳米晶体嵌入式Si氧化物电致发光（EL）器件的方法。 该方法提供高度掺杂的Si底部电极，并且形成覆盖电极的中带隙电绝缘膜。 在其中X小于2的中间带隙绝缘电介质膜上形成Si纳米晶体嵌入的SiOx膜层，并且透明顶部电极覆盖在Si纳米晶体嵌入的SiOx膜层上。 中间带隙电介质膜的带隙约为Si纳米晶体嵌入的SiOx膜的带隙的一半。 在一个方面，Si纳米晶体嵌入的SiO x膜具有约10电子伏特（eV）的带隙（Eg），并且中带隙绝缘电介质膜具有约5eV的带隙。 通过将高能隧道工艺分成两个较低能量的隧穿步骤，由于大功率热电子引起的潜在损害降低。

公开(公告)号：US07381595B2

公开(公告)日：2008-06-03

申请号：US11139726

申请日：2005-05-26

Applicant: Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

Inventor： Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

IPC: H01L21/00

CPC classification number: H01L29/78642 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/509 ,  H01L21/02164 ,  H01L21/0234 ,  H01L21/049 ,  H01L21/31612 ,  H01L29/66666 ,  H01L29/6675

Abstract: A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.

Abstract translation: 提供一种用于在垂直薄膜晶体管（V-TFT）制造工艺中形成低温垂直栅极绝缘体的方法。 该方法包括：形成具有垂直侧壁和顶表面的栅极，覆盖衬底绝缘层; 沉积覆盖栅极的氧化硅薄膜栅极绝缘体; 使用高密度等离子体源在低于400℃的温度下等离子体氧化栅极绝缘体; 形成覆盖所述栅极顶表面的第一源极/漏极区域; 在第一栅极侧壁附近形成覆盖衬底绝缘层的第二源极/漏极区域; 以及在位于第一和第二源极/漏极区之间的栅极绝缘体中形成覆盖第一栅极侧壁的沟道区。 当氧化硅薄膜栅极绝缘体沉积在栅极上覆盖Si氧化物层时，可以使用低温沉积工艺，从而可以获得大于65％的阶梯覆盖率。

公开(公告)号：US20080085559A1

公开(公告)日：2008-04-10

申请号：US11888491

申请日：2007-07-31

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele ,  Andrei Gindilis

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele ,  Andrei Gindilis

IPC: B01J19/12 ,  G01N33/00 ,  G21G5/00

CPC classification number: C12Q1/6813 ,  Y10S436/805

Abstract: A method of performing a fluid-material assay employing a device including at least one active pixel having a sensor with an assay site functionalized for selected fluid-assay material. The method includes exposing the pixel's sensor assay site to such material, and in conjunction with such exposing, and employing the active nature of the pixel, remotely requesting from the pixel's sensor assay site an assay-result output report. The method further includes, in relation to the employing step, creating, relative to the sensor's assay site in the at least one pixel, a predetermined, pixel-specific electromagnetic field environment.

Abstract translation: 使用包括至少一个具有传感器的活性像素的装置进行流体材料测定的方法，所述传感器具有用于所选流体测定材料功能化的测定位点。 该方法包括将像素的传感器测定位点暴露于这种材料，并结合这样的曝光，并采用像素的主动特性，从像素的传感器测定位点远程请求测定结果输出报告。 该方法还包括关于采用步骤，相对于至少一个像素中的传感器的测定位置产生预定的像素特定的电磁场环境。

公开(公告)号：US20080084372A1

公开(公告)日：2008-04-10

申请号：US11827174

申请日：2007-07-10

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

IPC: G09G3/36

CPC classification number: B01L3/5027 ,  B01L3/502707 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0819 ,  B01L2300/0877 ,  B01L2300/1822 ,  B01L2300/1827

Abstract: A pixel-by-pixel digitally-addressable, pixelated, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one functionalized, digitally-addressable assay sensor including at least one functionalized, digitally-addressable assay site which has been affinity-functionalized to respond to a selected, specific fluid-assay material, and (b) disposed operatively adjacent that sensor and its associated assay site, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the sensor and its associated assay site, a selected, ambient, electromagnetic field environment which is structured to assist, selectively and optionally only, in the reading-out of an assay-result response from the assay sensor and assay site.

Abstract translation: 逐像素可数字寻址，像素化，流体测定，包括优选地形成在玻璃或塑料基板上的多个像素的有源矩阵微结构，其中利用低温TFT和Si技术形成的每个像素包括（ a）至少一个功能化的，可数字寻址的测定传感器，其包括至少一个官能化的，可数字寻址的测定位点，其已经被亲和功能化以响应所选择的特定流体测定材料，和（b）可操作地邻近该传感器 以及其相关联的测定位点，可数字寻址和可激励的电磁场创建结构，其可选择性地激励以在传感器及其相关联的测定位点附近产生所选择的环境电磁场环境，其被构造为有选择地辅助 并且可选地仅在从测定传感器和测定位点读出测定结果响应中。

公开(公告)号：US07122488B2

公开(公告)日：2006-10-17

申请号：US10812591

申请日：2004-03-29

Applicant: Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

Inventor： Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

IPC: H01L21/469 ,  H01L21/31

CPC classification number: H01L21/049 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/509 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02274 ,  H01L21/045 ,  H01L21/31612

Abstract: Methods are provided for forming silicon dioxide (SiO2) on a silicon carbide (SiC) substrate. The method comprises: providing a SiC substrate; supplying an atmosphere including oxygen; performing a high-density (HD) plasma-based process; and, forming a SiO2 layer overlying the SiC substrate. Typically, performing the HD plasma-based process includes connecting a top electrode to an inductively coupled HD plasma source. In one aspect, SiO2 is grown on the SiC substrate. Then, an HD plasma oxidation process is performed that creates a reactive oxygen species and breaks the Si—C bonds in the SiC substrate, to form free Si and C atoms in the SiC substrate. The free Si atoms in the SiC substrate are bonded to the HD plasma-generated reactive oxygen species, and the SiO2 layer is grown.

Abstract translation: 提供了在碳化硅（SiC）衬底上形成二氧化硅（SiO 2）的方法。 该方法包括：提供SiC衬底; 提供包含氧气的气氛; 执行高密度（HD）等离子体工艺; 并且形成覆盖在SiC衬底上的SiO 2层。 通常，执行基于HD等离子体的工艺包括将顶部电极连接到电感耦合的HD等离子体源。 在一个方面，在SiC衬底上生长SiO 2。 然后，进行HD等离子体氧化处理，其产生活性氧物质并破坏SiC衬底中的Si-C键，以在SiC衬底中形成游离的Si和C原子。 SiC衬底中的自由Si原子与HD等离子体产生的活性氧结合，并且生长SiO 2层。

公开(公告)号：US08349745B2

公开(公告)日：2013-01-08

申请号：US12267698

申请日：2008-11-10

Applicant: Pooran Chandra Joshi ,  Hao Zhang ,  Jiandong Huang ,  Apostolos T. Voutsas

Inventor： Pooran Chandra Joshi ,  Hao Zhang ,  Jiandong Huang ,  Apostolos T. Voutsas

IPC: H01L21/31

CPC classification number: C23C16/30 ,  C23C16/5096 ,  C23C16/56

Abstract: A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for short wavelength luminescence applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including the element of N, O, or C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film has a peak photoluminescence (PL) at a wavelength in the range of 475 to 750 nanometers.

Abstract translation: 提供一种用于制造用于短波长发光应用的半导体纳米颗粒嵌入式Si绝缘膜的方法。 该方法提供底部电极，并沉积包含覆盖底部电极的N，O或C元素的半导体纳米颗粒嵌入的Si绝缘膜。 在退火之后，半导体纳米颗粒嵌入的Si绝缘膜在475至750纳米的波长范围内具有峰值光致发光（PL）。

公开(公告)号：US08236244B2

公开(公告)日：2012-08-07

申请号：US11827173

申请日：2007-07-10

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

IPC: G01J3/00

CPC classification number: B01J19/0046 ,  B01J2219/0061 ,  B01J2219/00614 ,  B01J2219/00659 ,  B01J2219/00675 ,  B01J2219/00677 ,  B01J2219/00689 ,  B01J2219/00711 ,  B01J2219/00722 ,  B82Y30/00 ,  C12Q1/6837 ,  C40B50/14 ,  C40B60/08 ,  G01N21/645 ,  G01N2021/6482 ,  Y10T29/49 ,  Y10T436/143333

Abstract: A digitally-addressable, pixelated, DNA fluid-assay, active-matrix micro-structure formed, utilizing low-temperature TFT and Si technology, on a substrate preferably made of glass or plastic, and including at least one pixel which is defined by (a) an addressable pixel site, (b) a sensor home structure disposed within that site for receiving and hosting a functionalized assay site possessing a DNA oligonucleotide probe, and (c) an addressable, pixel-site-specific, energy-field-producing functionalizer (preferably optical) operable to functionalize such a probe on the assay site. Each pixel may also include a pixel-integrated optical detector. Further disclosed are related methodology facets involving (1) the making of such a micro-structure (a) in a precursor form (without a functionalized probe), and thereafter (b) in a finalized/functionalized form (with such a probe), and (2) the ultimate use of a completed micro-structure in the performance of a DNA assay.

Abstract translation: 在优选由玻璃或塑料制成的衬底上，利用低温TFT和Si技术形成的可数字寻址，像素化，DNA流体测定，有源矩阵微结构，并且包括至少一个由（ a）可寻址像素位点，（b）设置在所述位置内的用于接收和承载具有DNA寡核苷酸探针的官能化测定位点的传感器家庭结构，和（c）可寻址的像素位点特异性能量场产生 功能化剂（优选光学）可操作以在测定位点官能化这种探针。 每个像素还可以包括像素集成的光学检测器。 进一步公开的是相关的方法学方面，其涉及（1）以前体形式（无官能化探针）制备这种微结构（a），此后（b）以最终/功能化形式（具有这种探针）， 和（2）在DNA测定的表现中最终使用完整的微结构。

公开(公告)号：US08007332B2

公开(公告)日：2011-08-30

申请号：US12187605

申请日：2008-08-07

Applicant: Pooran Chandra Joshi ,  Jiandong Huang ,  Apostolos T. Voutsas

Inventor： Pooran Chandra Joshi ,  Jiandong Huang ,  Apostolos T. Voutsas

IPC: H01J9/24

CPC classification number: C23C16/30 ,  C23C16/24 ,  C23C16/401 ,  C23C16/402 ,  C23C16/505 ,  C23C16/56 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/0262 ,  H01L21/31608 ,  H01L33/18

Abstract: A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for electroluminescence (EL) applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including an element selected from a group consisting of N and C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film is formed having an extinction coefficient (k) in a range of 0.01-1.0, as measured at about 632 nanometers (nm), and a current density (J) of greater than 1 Ampere per square centimeter (A/cm2) at an applied electric field lower than 3 MV/cm. In another aspect, the annealed semiconductor nanoparticle embedded Si insulating film has an index of refraction (n) in a range of 1.8-3.0, as measured at 632 nm, with a current density of greater than 1 A/cm2 at an applied electric field lower than 3 MV/cm.

Abstract translation: 提供了一种用于制造用于电致发光（EL）应用的半导体纳米颗粒嵌入的Si绝缘膜的方法。 该方法提供底部电极，并且沉积半导体纳米颗粒嵌入的Si绝缘膜，其包括选自N和C组成的组的元素，覆盖在底部电极上。 在退火之后，形成半导体纳米颗粒嵌入的Si绝缘膜，其消光系数（k）在0.01〜1.0的范围内，在大约632纳米（nm）测量，电流密度（J）大于1安培 在施加的电场低于3MV / cm下的平方厘米（A / cm 2）。 在另一方面，被退火的半导体纳米颗粒嵌入的Si绝缘膜的折射率（n）在632nm处测量的范围为1.8-3.0，在施加的电场下的电流密度大于1A / cm 2 低于3 MV / cm。

公开(公告)号：US07916986B2

公开(公告)日：2011-03-29

申请号：US12112767

申请日：2008-04-30

Applicant: Hao Zhang ,  Pooran Chandra Joshi ,  Apostolos T. Voutsas

Inventor： Hao Zhang ,  Pooran Chandra Joshi ,  Apostolos T. Voutsas

IPC: G02B6/26 ,  B05D5/06 ,  C23C14/48 ,  C23C14/16 ,  C23F1/00 ,  H01L21/00

CPC classification number: C23C16/30 ,  C23C16/56 ,  H01L21/02156 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/31608

Abstract: An erbium (Er)-doped silicon (Si) nanocrystalline embedded silicon oxide (SiOx) waveguide and associated fabrication method are presented. The method provides a bottom layer, and forms an Er-doped Si nanocrystalline embedded SiOx film waveguide overlying the bottom layer, having a minimum optical attenuation at about 1540 nanometers (nm). Then, a top layer is formed overlying the Er-doped SiOx film. The Er-doped SiOx film is formed by depositing a silicon rich silicon oxide (SRSO) film using a high density plasma chemical vapor deposition (HDPCVD) process and annealing the SRSO film. After implanting Er+ ions, the Er-doped SiOx film is annealed again. The Er-doped Si nanocrystalline SiOx film includes has a first refractive index (n) in the range of 1.46 to 2.30. The top and bottom layers have a second refractive index, less than the first refractive index.

Abstract translation: 提出了一种铒（Er）掺杂的硅（Si）纳米晶体嵌入式氧化硅（SiOx）波导及其制造方法。 该方法提供底层，并且形成覆盖底层的掺​​铒Si纳米晶体的包含SiOx的薄膜波导，在约1540纳米（nm）处具有最小的光衰减。 然后，形成覆盖Er掺杂的SiOx膜的顶层。 通过使用高密度等离子体化学气相沉积（HDPCVD）方法沉积富硅氧化物（SRSO）膜并退火SRSO膜来形成Er掺杂的SiOx膜。 在注入Er +离子后，再次对Er掺杂的SiOx膜进行退火。 掺铒Si纳米晶SiOx膜的第一折射率（n）在1.46〜2.30的范围内。 顶层和底层具有小于第一折射率的第二折射率。

公开(公告)号：US07786021B2

公开(公告)日：2010-08-31

申请号：US11264979

申请日：2005-11-02

Applicant: Pooran Chandra Joshi ,  Apostolos T. Voutsas

Inventor： Pooran Chandra Joshi ,  Apostolos T. Voutsas

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L29/4908 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/28008 ,  H01L21/31612 ,  H01L29/6675 ,  H01L29/78642

Abstract: A thin-film transistor (TFT) with a multilayer gate insulator is provided, along with a method for forming the same. The method comprises: forming a channel, first source/drain (S/D) region, and a second S/D region in a Silicon (Si) active layer; using a high-density plasma (HDP) source, growing a first layer of Silicon oxide (SiOx) from the Si active layer, to a first thickness, where x is less than, or equal to 2; depositing a second layer of SiOx having a second thickness, greater than the first thickness, overlying the first layer of SiOx; using the HDP source, additionally oxidizing the second layer of SiOx, wherein the first and second SiOx layers form a gate insulator; and, forming a gate electrode adjacent the gate insulator. In one aspect, the second Si oxide layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process with tetraethylorthosilicate (TEOS) precursors.

Abstract translation: 提供具有多层栅极绝缘体的薄膜晶体管（TFT）及其形成方法。 该方法包括：在硅（Si）有源层中形成沟道，第一源/漏（S / D）区和第二S / D区; 使用高密度等离子体（HDP）源，从Si活性层生长第一层氧化硅（SiO x）至第一厚度，其中x小于或等于2; 在SiOx的第一层上沉积具有大于第一厚度的第二厚度的第二SiO x层; 使用HDP源，另外氧化SiO x的第二层，其中第一和第二SiO x层形成栅极绝缘体; 并且形成与栅极绝缘体相邻的栅电极。 在一个方面，使用等离子体增强化学气相沉积（PECVD）法与原硅酸四乙酯（TEOS）前体沉积第二Si氧化物层。