公开(公告)号：US10748934B2

公开(公告)日：2020-08-18

申请号：US16115352

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Qingqing Liang ,  Stephen Alan Fanelli ,  Sinan Goktepeli

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/51

Abstract: An integrated circuit device includes a portion of a support wafer (e.g., a handle wafer), silicon on insulator layer, a first active device, and a second active device. The first active device has a first semiconductor thickness in a dielectric layer (e.g., a buried oxide layer). The first active device is on the SOI layer. The second active device has a second semiconductor thickness in the same dielectric layer as the first active device. The supporting wafer supports the first active device and the second active device. The second active device is also on the SOI layer. The first and second thicknesses are different from one another.

公开(公告)号：US10290579B2

公开(公告)日：2019-05-14

申请号：US15807169

申请日：2017-11-08

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Plamen Vassilev Kolev ,  Michael Andrew Stuber ,  Richard Hammond ,  Shiqun Gu ,  Steve Fanelli

IPC: H01L21/48 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/66 ,  H01L27/12 ,  H01L49/02 ,  H01L29/06 ,  H04B1/16 ,  H01L29/66 ,  H01L29/94

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

公开(公告)号：US20180316343A1

公开(公告)日：2018-11-01

申请号：US15582080

申请日：2017-04-28

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli

IPC: H03K17/16 ,  H04B1/44

CPC classification number: H03K17/165 ,  H03K17/687 ,  H03K17/693 ,  H03K17/74 ,  H03K2017/066 ,  H03K2217/0018 ,  H03K2217/0054

Abstract: Various aspects of this disclosure describe configuring and operating a transistor switch. Examples include a biasing circuit that contains a pair of diodes and a pair of resistors. The resistors may be placed in parallel by forward-biasing the pair of diodes. When the transistor is disabled (e.g., switch is open), gate-induced-drain-leakage (GIDL) current from the transistor, when flowing, may be split between each of the resistors to inhibit a voltage drop on the gate of the transistor, which may reduce harmonic distortion and/or increase the breakdown voltage of the transistor. The resistor values can be selected to ensure that the gate voltage of the transistor stays approximately equal to a negative bias voltage.

公开(公告)号：US10074942B2

公开(公告)日：2018-09-11

申请号：US15669096

申请日：2017-08-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli

IPC: H01L29/40 ,  H01L21/44 ,  H01R13/6599 ,  H01R13/6581 ,  H01L27/32

CPC classification number: H01R13/6599 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/66 ,  H01L27/1203 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/3272 ,  H01L29/408 ,  H01L29/4175 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78648 ,  H01L31/02164 ,  H01L2223/6677 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2924/1421 ,  H01R13/6581

Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include backside metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the backside metallization. The integrated RF circuit structure may further include front-side metallization coupled to the backside metallization with a via. The front-side metallization is arranged distal from the backside metallization. The front-side metallization, the via, and the backside metallization may at least partially enclose the active device.

公开(公告)号：US09812580B1

公开(公告)日：2017-11-07

申请号：US15257823

申请日：2016-09-06

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Steve Fanelli

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/06 ,  H01L23/522 ,  H01L23/66 ,  H01L21/762 ,  H01Q1/38 ,  H01Q1/24

CPC classification number: H01L29/78615 ,  H01L21/76251 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/66 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01Q1/241 ,  H01Q1/38

Abstract: An integrated circuit may include a gate, having gate fingers. The integrated circuit may also include a body, having semiconductor pillars interlocking with the gate fingers of the gate. The integrated circuit may also include a backside contact(s) coupled to the body. The integrated circuit may further include a backside metallization. The backside metallization may be coupled to the body through the backside contact(s).

公开(公告)号：US09466536B2

公开(公告)日：2016-10-11

申请号：US14451342

申请日：2014-08-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Stuart B. Molin ,  George P. Imthurn

IPC: H01L21/30 ,  H01L21/00 ,  H01L21/46 ,  H01L21/84 ,  H01L21/762 ,  H01L21/3213 ,  H01L23/48 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76256 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for manufacturing semiconductor-on-insulator (SOI) integrated circuits are disclosed. An SOI wafer is provided having a first surface and a second surface. The substrate of the SOI wafer forms the second surface. A transistor is formed in the semiconductor layer of the SOI wafer. A handle wafer is bonded to the first surface of the SOI wafer. The substrate layer is then removed to expose a back surface of the buried insulator of the SOI wafer. Conductive material is deposited on the SOI wafer that covers the back surface of the buried insulator. The conductive material is patterned to form a second gate electrode for the transistor on the back surface of the insulator.

Abstract translation: 公开了制造绝缘体上半导体（SOI）集成电路的方法。 提供具有第一表面和第二表面的SOI晶片。 SOI晶片的衬底形成第二表面。 晶体管形成在SOI晶片的半导体层中。 把手晶片结合到SOI晶片的第一表面。 然后去除衬底层以暴露SOI晶片的埋入绝缘体的背表面。 导电材料沉积在覆盖掩埋绝缘体背面的SOI晶片上。 将导电材料图案化以形成用于绝缘体背面上的晶体管的第二栅电极。

公开(公告)号：US11081582B2

公开(公告)日：2021-08-03

申请号：US16788197

申请日：2020-02-11

Applicant: QUALCOMM Incorporated

Inventor： Qingqing Liang ,  Ravi Pramod Kumar Vedula ,  Sivakumar Kumarasamy ,  George Pete Imthurn ,  Sinan Goktepeli

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.

公开(公告)号：US10903357B2

公开(公告)日：2021-01-26

申请号：US16152105

申请日：2018-10-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  George Pete Imthurn ,  Sivakumar Kumarasamy

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/40 ,  H01L29/786 ,  H04B1/00 ,  H04B1/52 ,  H01L27/12 ,  H04B1/38

Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.

公开(公告)号：US10707866B1

公开(公告)日：2020-07-07

申请号：US16230884

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： Qingqing Liang ,  Ravi Pramod Kumar Vedula ,  George Peter Imthurn ,  Christopher Nelles Brindle ,  Sinan Goktepeli

IPC: H03K17/687 ,  H03K17/10 ,  H03K17/284 ,  H01L27/12 ,  H01L23/50 ,  H01L21/76 ,  H01L21/84 ,  H01L23/66 ,  H01L21/762

Abstract: A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.

公开(公告)号：US10608124B2

公开(公告)日：2020-03-31

申请号：US15957484

申请日：2018-04-19

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Fabio Alessio Marino ,  Narasimhulu Kanike ,  Plamen Vassilev Kolev ,  Qingqing Liang ,  Paolo Menegoli ,  Francesco Carobolante ,  Aristotele Hadjichristos

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/45

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.