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公开(公告)号：US11450356B2
公开(公告)日：2022-09-20
申请号：US16828591
申请日：2020-03-24
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , John Eric Linstadt , Carl W. Werner
Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.
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公开(公告)号：US11133843B1
公开(公告)日：2021-09-28
申请号：US17074949
申请日：2020-10-20
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Carl W. Werner
Abstract: An integrated-circuit output driver generates, in response to an input signal constrained to a first voltage range, a control signal at one of two voltage levels according to a data bit conveyed in the input signal, the two voltages levels defining upper and lower levels of a second voltage range substantially larger than the first voltage range. The output driver generates an output-drive signal constrained to a third voltage range according to the one of the two voltage levels of the control signal, the third voltage range being substantially smaller than the second voltage range.
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公开(公告)号：US10892725B1
公开(公告)日：2021-01-12
申请号：US16700689
申请日：2019-12-02
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Carl W. Werner , John Eric Linstadt
Abstract: A signal amplifier is distributed between first and second IC devices and includes a low-power input stage disposed within the first IC device, a bias-current source disposed within the second IC device and an output stage disposed within the second IC device. The output stage includes a resistance disposed within the second IC device and having a first terminal coupled to a drain terminal of a transistor within the input stage via a first signaling line that extends between the first and second IC devices.
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24.发明申请公开(公告)号：US20190020373A1
公开(公告)日：2019-01-17
申请号：US15890341
申请日：2018-02-06
Applicant: Rambus Inc.
Inventor： John W. Poulton , Frederick A. Ware , Carl W. Werner
IPC: H04B3/56 , H04L25/02 , H04B3/54 , H03F3/24 , G06F13/40 , H04B10/073 , H04B10/40 , H04B10/50 , H04B1/04
Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
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公开(公告)号：US20170222845A1
公开(公告)日：2017-08-03
申请号：US15400647
申请日：2017-01-06
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett , Carl W. Werner
CPC classification number: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
Abstract: An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.
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Patent Agency Ranking
26.发明授权公开(公告)号：US09350421B2
公开(公告)日：2016-05-24
申请号：US14072307
申请日：2013-11-05
Applicant: Rambus Inc.
Inventor： John W. Poulton , Frederick A. Ware , Carl W. Werner
CPC classification number: H04B3/56 , G06F13/4072 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2924/15311 , H03F3/24 , H04B3/54 , H04B10/0731 , H04B10/40 , H04B10/50 , H04B2001/0408 , H04L25/0272 , H01L2924/00014
Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
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公开(公告)号：US08903031B2
公开(公告)日：2014-12-02
申请号：US13897267
申请日：2013-05-17
Applicant: Rambus Inc.
Inventor： Carl W. Werner
CPC classification number: H04L7/0331 , H03D13/004 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033
Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
Abstract translation: 时钟恢复电路包括用于测量来自压控振荡器（VCO）的第一时钟信号与数据信号之间的相位差的第一相位检测器。 基于该相位差响应于控制信号的移相器调整输入时钟信号的相位以产生第二时钟信号。 测量第一时钟信号和第二时钟信号之间的相位差，并将所得到的信号进行低通滤波，以得到用于控制VCO的控制信号。 包括VCO的锁相环滤除抖动。
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公开(公告)号：US20140286389A1
公开(公告)日：2014-09-25
申请号：US14158675
申请日：2014-01-17
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, JR. , Carl W. Werner
IPC: H04L25/03
CPC classification number: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
Abstract: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.
Abstract translation: 集成电路器件包括具有输入端的读出放大器，用于接收表示当前位的当前信号。 读出放大器将产生关于当前位的逻辑电平的判定。 该集成电路器件还包括一个电路，用于通过向读出放大器的输入端施加代表先前位的先前信号的一部分来对读出放大器的输入进行预充电。 集成电路器件还包括耦合到读出放大器以输出逻辑电平的锁存器。
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公开(公告)号：US11996160B2
公开(公告)日：2024-05-28
申请号：US17892291
申请日：2022-08-22
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , John Eric Linstadt , Carl W. Werner
CPC classification number: G11C7/04 , G06F1/12 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/50012 , G11C2207/2254 , H03K5/15 , H10N60/12
Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.
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公开(公告)号：US11811397B1
公开(公告)日：2023-11-07
申请号：US17480026
申请日：2021-09-20
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Carl W. Werner
IPC: H03K17/92 , H03K19/173 , G06F1/26 , H03K19/195 , F25D29/00
CPC classification number: H03K17/92 , F25D29/001 , G06F1/263 , H03K19/1733 , H03K19/1952
Abstract: An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data output contacts. The array of switch cells receives the control signals directly from the control signal contacts and response to the control signals by switchably interconnecting the data input contacts with selected ones of the data output contacts.
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