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公开(公告)号：US20210385932A1
公开(公告)日：2021-12-09
申请号：US17163945
申请日：2021-02-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dohyung Kim , Seongchul Hong , Insung Kim , Jinhong Park , Jungchul Lee
IPC: H05G2/00 , H01L21/268
Abstract: Disclosed are semiconductor manufacturing apparatuses and operating methods thereof. The semiconductor manufacturing apparatus includes an oscillation unit that includes a first seed laser, a second seed laser, and a seed module, wherein the first seed laser oscillates a first pulse, and wherein the second seed laser oscillates a second pulse, and an extreme ultraviolet generation unit configured to use the first and second pulses to generate extreme ultraviolet light. The seed module includes a plurality of mirrors configured to allow the first and second pulses to travel along first and second paths, respectively, and a pulse control optical system including a first optical element, a second optical element, and a third optical element. The pulse control optical system is on the second path that does not overlap the first path. The third optical element includes a lens between the first optical element and the second optical element.
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公开(公告)号：US09406369B2
公开(公告)日：2016-08-02
申请号：US14325867
申请日：2014-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Hyun Seok , Dohyung Kim , Kwangseop Kim , Young-Ho Lee
IPC: H01L23/34 , G11C11/401 , G11C5/02 , G11C5/04
CPC classification number: G11C11/401 , G11C5/025 , G11C5/04
Abstract: A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins.
Abstract translation: 存储模块包括印刷电路板; 第一存储器芯片，沿着第一列与印刷电路板的长轴平行设置; 第二存储器芯片沿着第二列与印刷电路板的长轴平行布置; 以及设置在所述第一存储器芯片和所述第二存储器芯片之间的无源元件，其中所述无源元件连接在所述第一存储器芯片和所述第二存储器芯片中的每一个的输入/输出引脚之间。
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公开(公告)号：US20240194266A1
公开(公告)日：2024-06-13
申请号：US18518496
申请日：2023-11-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jiwon Kim , Jiyoung Kim , Woosung Yang , Dohyung Kim , Sukkang Sung
IPC: G11C16/08 , H01L23/522 , H01L23/528 , H01L25/065 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B80/00
CPC classification number: G11C16/08 , H01L23/5226 , H01L23/5283 , H01L25/0652 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/06506
Abstract: A semiconductor device includes a first substrate structure including a first decoder circuit region, a second decoder circuit region, and a page buffer circuit region, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a first cell structure that includes first horizontally extending gate electrodes, and a second cell structure that includes second horizontally extending gate electrodes. The second cell structure is disposed below the first cell structure. A first stair structure is disposed to one side of the first and second cell structures, and a second stair structure is disposed to a second side opposite the first side. a dummy structure is disposed below the first stair structure. First contact plugs pass through the first stair structure and the first dummy structure and are respectively connected to the first gate electrodes, and second contact plugs pass through the second stair structure and are respectively connected to the second gate electrodes.
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24.发明公开公开(公告)号：US20240023337A1
公开(公告)日：2024-01-18
申请号：US18118776
申请日：2023-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jiwon Kim , Jiyoung Kim , Dohyung Kim , Sukkang Sung , Takuya Futatsuyama
IPC: H10B43/40 , H10B43/10 , H01L23/522 , H01L23/528 , H10B43/35 , H10B43/27
CPC classification number: H10B43/40 , H10B43/10 , H01L23/5226 , H01L23/5283 , H10B43/35 , H10B43/27
Abstract: Disclosed is a semiconductor device comprising a peripheral circuit structure on a first substrate, a cell array structure on the peripheral circuit structure, and a backside structure on the cell array structure. The cell array structure includes a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked, through plugs that extend in a first direction through the stack structure and each including a first surface adjacent to the backside structure and a second surface opposite to the first surface, a middle circuit structure between the stack structure and the peripheral circuit structure and connected to the peripheral circuit structure, and a connection plug connected to the middle circuit structure and the backside structure. The through plugs include a first through plug connected through the first surface to the backside structure, and a second through plug connected through the second surface to the middle circuit structure.
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公开(公告)号：US11828952B2
公开(公告)日：2023-11-28
申请号：US17218891
申请日：2021-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dohyung Kim , Seongchul Hong , Kyungsik Kang , Kyungbin Park , Motoshi Sakai , Seungkoo Lee , Jungchul Lee
CPC classification number: G02B27/1073 , G02B27/106 , G02B27/108 , G02B27/141 , G03F7/70191 , H01S3/0071 , H01S3/2308 , H01S3/2383 , H05G2/008 , H01S3/2232
Abstract: A light source capable of operating third and fourth reflection mirrors included in a beam splitting device in conjunction with movements of first and second reflection mirrors included in a beam transfer device and an optical assembly, respectively. The third and fourth reflection mirrors are disposed on optical paths of a pre-pulse and a main pulse emitted from first and second pulse generators, respectively. The light source operates the third and fourth reflection mirrors to offset an excessive compensation of the main pulse caused in a process of compensating for an optical path error of the pre-pulse. The light source may be included in an extreme ultraviolet light source system.
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Patent Agency Ranking
公开(公告)号：US11812547B2
公开(公告)日：2023-11-07
申请号：US17356940
申请日：2021-06-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dongyoon Seo , Sangkeun Kwak , Dohyung Kim , Kyeongseon Park , Hwanwook Park , Wonseop Lee , Daae Heo
CPC classification number: H05K1/0263 , H05K1/0296 , H05K1/142 , H05K2201/10159
Abstract: A memory module including: a first printed circuit board; a first socket and a second socket; and a daisy chain pattern formed in a first region of the first printed circuit board and connected to the first socket and the second socket, wherein an electrical signal on the daisy chain pattern is transferred to a host device when the first socket and the second socket are connected to the host device.
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公开(公告)号：US11758652B2
公开(公告)日：2023-09-12
申请号：US17360417
申请日：2021-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dongyoon Seo , Geunje Park , Dohyung Kim , Hwanwook Park , Dongmin Jang , Jaeseok Jang
CPC classification number: H05K1/111 , H05K1/181 , H05K2201/09745
Abstract: A printed circuit board (PCB) includes: an insulation substrate; a first pad on the insulation substrate; and a second pad on the insulation substrate and spaced apart from the first pad, wherein the second pad has a size substantially the same as a size of the first pad, wherein the first pad includes a first recess configured to receive a first electrode of a passive element, wherein the second pad includes a second recess receiving a second electrode of the passive element, wherein the first recess has a depth substantially the same as a thickness of the first pad, wherein the second recess has a depth substantially the same as a thickness of the second pad, wherein each of the first recess and the second recess exposes an upper surface of the insulation substrate.
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公开(公告)号：US11477880B2
公开(公告)日：2022-10-18
申请号：US17337850
申请日：2021-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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公开(公告)号：US20220066225A1
公开(公告)日：2022-03-03
申请号：US17218891
申请日：2021-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dohyung Kim , Seongchul Hong , Kyungsik Kang , Kyungbin Park , Motoshi Sakai , Seungkoo Lee , Jungchul Lee
Abstract: A light source capable of operating third and fourth reflection mirrors included in a beam splitting device in conjunction with movements of first and second reflection mirrors included in a beam transfer device and an optical assembly, respectively. The third and fourth reflection mirrors are disposed on optical paths of a pre-pulse and a main pulse emitted from first and second pulse generators, respectively. The light source operates the third and fourth reflection mirrors to offset an excessive compensation of the main pulse caused in a process of compensating for an optical path error of the pre-pulse. The light source may be included in an extreme ultraviolet light source system.
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30.发明授权公开(公告)号：US09941135B2
公开(公告)日：2018-04-10
申请号：US14840114
申请日：2015-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sejun Park , Dohyung Kim , Jaihyung Won , Sangho Roh , Eunsol Shin , Seung Moo Lee , Gyuwan Choi
IPC: H01L21/308 , H01L21/311 , H01L21/762 , C23C16/26 , C23C16/56 , H01L21/02 , H01L29/423 , H01L27/108
CPC classification number: H01L21/3081 , C23C16/26 , C23C16/56 , H01L21/02115 , H01L21/02266 , H01L21/02274 , H01L21/31144 , H01L21/762 , H01L21/76224 , H01L27/10814 , H01L27/10852 , H01L27/10855 , H01L27/10888 , H01L29/4236
Abstract: A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N2O). A source of carbon and the nitrous oxide (N2O) are introduced to the substrate under a plasma ambient of an inert gas. The amorphous carbon layer has a nitrogen content ranging from about 0.05 at % to about 30 at % and an oxygen content ranging from about 0.05 at % to about 10 at %. In forming a semiconductor device, the hard mask layer is patterned, and a target layer beneath the hard mask layer is etched using the patterned hard mask layer as an etch mask.
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