公开(公告)号：US11250894B2

公开(公告)日：2022-02-15

申请号：US17145941

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

公开(公告)号：US20210311821A1

公开(公告)日：2021-10-07

申请号：US17088900

申请日：2020-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Namsung KIM ,  Sanguhn CHA ,  Jaeyoun Youn ,  Kijun Lee

IPC: G06F11/10 ,  H01L25/065

Abstract: A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

公开(公告)号：US10671464B2

公开(公告)日：2020-06-02

申请号：US15850604

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonhee Oh ,  Je Min Ryu ,  Reum Oh ,  Jaeyoun Youn

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/0802 ,  G11C16/10 ,  G06F11/10 ,  G11C29/48 ,  G11C29/04

Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.

公开(公告)号：US20180189127A1

公开(公告)日：2018-07-05

申请号：US15850604

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonhee Oh ,  Je Min Ryu ,  Reum Oh ,  Jaeyoun Youn

IPC: G06F11/07 ,  G11C16/10 ,  G11C29/48 ,  G06F12/0802

CPC classification number: G06F11/0721 ,  G06F11/0736 ,  G06F11/1048 ,  G06F12/0802 ,  G11C16/10 ,  G11C29/48 ,  G11C2029/0409

Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.

公开(公告)号：US12002543B2

公开(公告)日：2024-06-04

申请号：US18299440

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

公开(公告)号：US11860803B2

公开(公告)日：2024-01-02

申请号：US17685987

申请日：2022-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: G06F13/38 ,  G06F13/16 ,  H01L25/065 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F13/1668 ,  H01L25/0657 ,  G11C7/10 ,  G11C8/10 ,  H01L2225/06541

Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

公开(公告)号：US11620504B2

公开(公告)日：2023-04-04

申请号：US16892637

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo Yu ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: G06N3/063 ,  G06N3/08 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/54 ,  G11C11/56

Abstract: A neuromorphic device includes a memory cell array that includes first memory cells corresponding to a first address and storing first weights and second memory cells corresponding to a second address and storing second weights, and a neuron circuit that includes an integrator summing first read signals from the first memory cells and an activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.

公开(公告)号：US11127713B2

公开(公告)日：2021-09-21

申请号：US16926189

申请日：2020-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/66

Abstract: High bandwidth memories and systems including the same may include a buffer die, a plurality of memory dies stacked on the buffer die, a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, and a plurality of signal line groups. Each of the plurality of dummy bump groups includes dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other. Each of the signal line groups includes a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals applied to an input dummy bump of each of the plurality of dummy bump groups via sequential transmission through the plurality of dummy bumps to an output dummy bump during a bump crack test operation.

公开(公告)号：US10784184B2

公开(公告)日：2020-09-22

申请号：US16263408

申请日：2019-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Rho ,  Chisung Oh ,  Kyomin Sohn ,  Yong-Ki Kim ,  Jong-Ho Moon ,  SeungHan Woo ,  Jaeyoun Youn

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.

公开(公告)号：US09747998B2

公开(公告)日：2017-08-29

申请号：US14462843

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua Kim ,  Dongsoo Kang ,  Chulwoo Park ,  Jun Hee Yoo ,  Hak-Soo Yu ,  Jaeyoun Youn ,  Sung Hyun Lee ,  Jinsu Jung ,  Hyojin Choi

IPC: G11C17/16 ,  G11C29/02 ,  G11C29/42 ,  G11C29/44 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

Abstract: A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.