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202 条记录 (耗时 0.043 秒)

    SEMICONDUCTOR MEMORY DEVICE
    22.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20080181026A1

    公开(公告)日：2008-07-31

    申请号：US11963831

    申请日：2007-12-22

    申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    IPC分类号： G11C7/08

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

    摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

    摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

    Semiconductor memory device
    24.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07609572B2

    公开(公告)日：2009-10-27

    申请号：US11963831

    申请日：2007-12-22

    申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

    摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

    摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

    Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed
    28.
    再颁专利
    Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed 有权
    大容量半导体存储器，具有改进的子放大器布局，以提高速度

    公开(公告)号：USRE42659E1

    公开(公告)日：2011-08-30

    申请号：US11759316

    申请日：2007-06-07

    申请人： Tsugio Takahashi ,  Goro Kitsukawa ,  Takesada Akiba ,  Yasushi Kawase ,  Masayuki Nakamura

    发明人： Tsugio Takahashi ,  Goro Kitsukawa ,  Takesada Akiba ,  Yasushi Kawase ,  Masayuki Nakamura

    IPC分类号： G11C8/00

    CPC分类号： H01L27/10805 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/105

    摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

    摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及指定的子公共I / O线选择性地连接的主要公共I / O。

    ZQ calibration circuit and a semiconductor device including a ZQ calibration circuit
    29.
    发明授权
    ZQ calibration circuit and a semiconductor device including a ZQ calibration circuit 有权
    ZQ校准电路和包括ZQ校准电路的半导体器件

    公开(公告)号：US07839159B2

    公开(公告)日：2010-11-23

    申请号：US11585108

    申请日：2006-10-24

    申请人： Masayuki Nakamura ,  Hideyuki Yoko

    发明人： Masayuki Nakamura ,  Hideyuki Yoko

    IPC分类号： G01R31/26

    CPC分类号： H04L25/0278 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

    摘要： A ZQ calibration command is internally generated from an external command different from a ZQ calibration command so as to automatically perform an additional ZQ calibration operation. A command interval between an inputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from the ZQ calibration command is preferably a self-refreshed command. The addition of the ZQ calibration operation shortens intervals between ZQ calibration operations. Thus, it is possible to obtain a ZQ calibration circuit capable of performing a ZQ calibration operation more accurately.

    摘要翻译： ZQ校准命令在内部从与ZQ校准命令不同的外部命令生成，以便自动执行附加的ZQ校准操作。 有效地采用输入命令和下一命令之间的命令间隔来获得ZQ校准周期。 与ZQ校准命令不同的外部命令优选为自刷新命令。 添加ZQ校准操作可缩短ZQ校准操作之间的间隔。 因此，可以更精确地获得能够执行ZQ校准操作的ZQ校准电路。

    MEMORY ACCESS CONTROL CIRCUIT AND IMAGE PROCESSING SYSTEM
    30.
    发明申请
    MEMORY ACCESS CONTROL CIRCUIT AND IMAGE PROCESSING SYSTEM 有权
    存储器访问控制电路和图像处理系统

    公开(公告)号：US20100123728A1

    公开(公告)日：2010-05-20

    申请号：US12608322

    申请日：2009-10-29

    申请人： Akihiro KAWAHARA ,  Makoto Adachi ,  Kouji Nishikawa ,  Masayuki Nakamura ,  Motonobu Mamiya ,  Kae Yamashita

    发明人： Akihiro KAWAHARA ,  Makoto Adachi ,  Kouji Nishikawa ,  Masayuki Nakamura ,  Motonobu Mamiya ,  Kae Yamashita

    IPC分类号： G06F13/00 ,  G06F12/16

    CPC分类号： G09G5/397 ,  G09G5/363 ,  G09G5/393

    摘要： A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.

    摘要翻译： 存储器访问控制电路包括第一内部寄存器，地址发送单元，其将第一内部寄存器的状态设置为第一状态以发送第一地址，并将第一内部寄存器的状态设置为第二状态，以发送第二内部寄存器 地址，第二内部寄存器，数据接收单元，其将第二内部寄存器的状态设置为第三状态，以接收对应于第一地址的第一数据，对延迟的第一数据执行数据处理，设置第二内部寄存器的状态 内部寄存器到第四状态以接收对应于第二地址的第二数据，并且在延迟给定延迟时间的第二数据之后对第二数据执行数据处理，第一备份单元和第二备份单元。