公开(公告)号：US11837550B2

公开(公告)日：2023-12-05

申请号：US17215079

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/83 ,  H01L2021/6006 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/27334 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1533 ,  H01L2924/15311 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20230378075A1

公开(公告)日：2023-11-23

申请号：US18230829

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49805 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/3128 ,  H01L25/105 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L24/83 ,  H01L2924/1533 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/143 ,  H01L2924/141 ,  H01L2224/92244 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/27334 ,  H01L2224/214 ,  H01L24/32 ,  H01L2021/6006

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US11502050B2

公开(公告)日：2022-11-15

申请号：US17170624

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L21/02 ,  H01L23/532 ,  H01L23/525 ,  H01L23/00

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US20210384294A1

公开(公告)日：2021-12-09

申请号：US17445692

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US11177237B2

公开(公告)日：2021-11-16

申请号：US16714823

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

Abstract: A manufacturing method for semiconductor packages is provided. Chips are provided on a carrier. Through interlayer vias are formed over the carrier to surround the chips. A molding compound is formed over the carrier to partially and laterally encapsulate the chip and the through interlayer vias. The molding compound comprises pits on a top surface thereof. A polymeric molding compound is formed on the molding compound to fill the pits of the molding compound.

公开(公告)号：US20210225723A1

公开(公告)日：2021-07-22

申请号：US17201856

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20210066269A1

公开(公告)日：2021-03-04

申请号：US16866561

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Yang ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Yu-Hao Chen

IPC: H01L25/16 ,  H01L23/498

Abstract: Semiconductor packages are provided. The semiconductor package includes a first redistribution layer structure, a photonic integrated circuit, an electronic integrated circuit, a waveguide and a memory. The photonic integrated circuit is disposed over and electrically connected to the first redistribution layer structure, and includes an optical transceiver and an optical coupler. The electronic integrated circuit is disposed over and electrically connected to the first redistribution layer structure. The waveguide is optically coupled to the optical coupler. The memory is electrically connected to the electronic integrated circuit.

公开(公告)号：US20210020607A1

公开(公告)日：2021-01-21

申请号：US16513739

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsaing-Pin Kuan ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Chun-Yen Lan ,  Kai-Ming Chiang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/488 ,  H01L25/00 ,  H01L23/538 ,  H01L23/28

Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.

公开(公告)号：US20200350197A1

公开(公告)日：2020-11-05

申请号：US16934394

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Hui-Min Huang ,  Ai-Tee Ang ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/683 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

公开(公告)号：US10535609B2

公开(公告)日：2020-01-14

申请号：US16020030

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.