公开(公告)号：US20190035455A1

公开(公告)日：2019-01-31

申请号：US15800443

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro FUJIWARA ,  Chih-Yu Lin ,  Sahil Preet Singh ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C7/12 ,  G11C8/08 ,  G11C5/14 ,  G11C11/4074 ,  H03K19/013

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US10153038B2

公开(公告)日：2018-12-11

申请号：US15911824

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/12 ,  G11C11/412 ,  G11C7/16 ,  G11C8/16 ,  G11C7/18

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US10083739B2

公开(公告)日：2018-09-25

申请号：US14334935

申请日：2014-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Yen-Huei Chen ,  Ching-Wei Wu

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  H01L27/11 ,  G11C7/10 ,  H01L25/065 ,  G11C8/16 ,  G11C11/412 ,  H01L27/06 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/522 ,  H01L25/00 ,  G11C11/418 ,  G11C11/40

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1075 ,  G11C7/1096 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  G11C11/413 ,  G11C11/418 ,  H01L21/768 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.

公开(公告)号：US20180197601A1

公开(公告)日：2018-07-12

申请号：US15911824

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/419 ,  G11C11/412 ,  G11C8/16 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12

CPC classification number: G11C11/419 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12 ,  G11C8/16 ,  G11C11/412 ,  G11C2207/005

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US09922700B2

公开(公告)日：2018-03-20

申请号：US15162711

申请日：2016-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/12 ,  G11C11/412 ,  G11C7/16 ,  G11C8/16 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12 ,  G11C8/16 ,  G11C11/412 ,  G11C2207/005

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US09886996B2

公开(公告)日：2018-02-06

申请号：US15222914

申请日：2016-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Mahmut Sinangil

IPC: G11C11/412 ,  G11C11/418 ,  H01L27/11 ,  G11C11/419 ,  G11C8/14

CPC classification number: G11C11/412 ,  G11C8/14 ,  G11C11/418 ,  G11C11/419 ,  H01L27/1104

Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled to the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled to the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.

公开(公告)号：US20170272075A1

公开(公告)日：2017-09-21

申请号：US15073948

申请日：2016-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Yuan Chen ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh ,  Che-Ju Yeh

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.

公开(公告)号：US09552873B2

公开(公告)日：2017-01-24

申请号：US15016172

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Yen-Huei Chen

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/14

CPC classification number: G11C11/419 ,  G11C7/14

Abstract: A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data.

Abstract translation: 一种设备包括存储单元，参考存储单元和感测单元。 参考存储单元被配置为存储第一位数据和第四位数据被配置为高逻辑状态的第一位数据，第二位数据，第三位数据和第四位数据，并且第二位数据 并且第三位数据被配置为低逻辑状态。 感测单元被配置为根据第一位数据，第二位数据，第三位数据和第四位数据读取存储在一个存储器单元中的位数据。

公开(公告)号：US09208854B2

公开(公告)日：2015-12-08

申请号：US14098567

申请日：2013-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Yen-Huei Chen

IPC: G11C11/00 ,  G11C11/413 ,  H01L27/11 ,  G11C7/10 ,  H01L25/065 ,  G11C11/40

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1075 ,  G11C7/1096 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  G11C11/413 ,  G11C11/418 ,  H01L21/768 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three dimensional dual-port bit cell generally comprises a first portion of a latch disposed on a first tier, wherein the first portion includes a plurality of first port elements. A second portion of the latch is disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a plurality of second port elements.

Abstract translation: 三维双端口位单元通常包括设置在第一层上的锁存器的第一部分，其中第一部分包括多个第一端口元件。 闩锁的第二部分设置在使用至少一个通孔相对于第一层垂直堆叠的第二层上，其中第二部分包括多个第二端口元件。

公开(公告)号：US09064799B2

公开(公告)日：2015-06-23

申请号：US14079671

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Li-Chun Tien

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.

Abstract translation: 一种方法包括在半导体衬底的有效区域上形成第一多个指状物。 第一多个指状物中的每一个具有在与有源区域的宽度方向平行的方向上延伸的相应长度。 第一多个指状物形成至少一个晶体管的至少一个栅极，该晶体管具有由有源区域的一部分形成的源极和漏极。 第一虚设多晶硅结构形成在第一多个指状物的外部之一和半导体衬底的第一边缘之间的有源区域的一部分上。 第二虚设多晶硅结构在第一虚设多晶硅结构和半导体衬底的第一边缘之间的半导体衬底之上。