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    CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY
    21.
    发明申请
    CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY 审中-公开

    公开(公告)号：US20190333921A1

    公开(公告)日：2019-10-31

    申请号：US16506207

    申请日：2019-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

    IPC: H01L27/11521 ,  H01L21/762 ,  H01L27/11548 ,  H01L27/11534 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11526

    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

    CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY
    22.
    发明申请
    CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY 审中-公开

    公开(公告)号：US20190057972A1

    公开(公告)日：2019-02-21

    申请号：US16167879

    申请日：2018-10-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

    IPC: H01L27/11521 ,  H01L29/423 ,  H01L27/11548 ,  H01L27/11534 ,  H01L21/28 ,  H01L27/11526 ,  H01L21/762 ,  H01L23/528

    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

    Cell boundary structure for embedded memory
    23.
    发明授权
    Cell boundary structure for embedded memory 有权

    公开(公告)号：US10134748B2

    公开(公告)日：2018-11-20

    申请号：US15694098

    申请日：2017-09-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

    IPC: H01L21/762 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/423 ,  H01L23/528

    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

    COMPOSITE SPACER FOR SILICON NANOCRYSTAL MEMORY STORAGE
    24.
    发明申请
    COMPOSITE SPACER FOR SILICON NANOCRYSTAL MEMORY STORAGE 有权
    用于硅纳米晶体存储器的复合间隔器

    公开(公告)号：US20160049420A1

    公开(公告)日：2016-02-18

    申请号：US14461565

    申请日：2014-08-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hsing Chang ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

    IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L21/02601 ,  H01L21/02532 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

    Abstract: Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact.

    Abstract translation: 一些实施例涉及包括设置在控制栅极和选择栅极之间的电荷捕获层的存储器件。 封盖结构设置在控制栅极的上表面上，并且复合间隔物设置在控制栅极的面向源的侧壁表面上。 封盖结构和复合间隔物在用于与存储器件的接触形成的一个以上蚀刻工艺期间防止对控制栅极的损坏。 为了进一步限制或防止选择栅极侧壁蚀刻，一些实施例提供沿着选择栅极的面向排水的侧壁表面设置的附加衬垫氧化物层。 衬里氧化物层被配置为蚀刻停止层，以防止在一个或多个蚀刻工艺期间蚀刻选择栅极。 结果，一个或多个蚀刻工艺离开控制栅极并基本上完整地选择栅极。

    RRAM cell with bottom electrode
    26.
    发明授权
    RRAM cell with bottom electrode 有权
    带底电极的RRAM电池

    公开(公告)号：US09178144B1

    公开(公告)日：2015-11-03

    申请号：US14252111

    申请日：2014-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Yu-Hsing Chang ,  Ru-Liang Lee

    IPC: H01L45/00 ,  H01L23/538

    CPC classification number: H01L45/1253 ,  H01L23/538 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell.

    Abstract translation: 本公开涉及具有底部电极的电阻随机存取存储器（RRAM）单元，其在不使用绝缘侧壁间隔件的情况下提供RRAM单元内的低泄漏电流，以及相关联的形成方法。 在一些实施例中，RRAM单元具有设置在由下层电介质（ILD）层围绕的下金属互连层上的底电极。 底部电介质层设置在下部金属互连层和/或下部ILD层上。 具有可变电阻的电介质数据存储层位于底部电介质层和底部电极之上，并且顶部电极设置在电介质数据存储层上。 将电介质数据存储层放置在底部电介质层上增加了底部和顶部电极之间的泄漏路径距离，从而为RRAM单元提供了低泄漏电流。

    Cell boundary structure for embedded memory
    29.
    发明授权
    Cell boundary structure for embedded memory 有权

    公开(公告)号：US10535671B2

    公开(公告)日：2020-01-14

    申请号：US16506207

    申请日：2019-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

    IPC: H01L21/762 ,  H01L27/11521 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L27/11526 ,  H01L29/423 ,  H01L23/528

    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

    Cell boundary structure for embedded memory
    30.
    发明授权
    Cell boundary structure for embedded memory 有权

    公开(公告)号：US10461089B2

    公开(公告)日：2019-10-29

    申请号：US16167879

    申请日：2018-10-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

    IPC: H01L27/11521 ,  H01L21/762 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L23/528

    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

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