公开(公告)号：US20190131414A1

公开(公告)日：2019-05-02

申请号：US15800474

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/265

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US10101295B2

公开(公告)日：2018-10-16

申请号：US15386545

申请日：2016-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsien Chang ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Ching-Hui Lin

IPC: G01N27/403 ,  G01N27/414 ,  H01L23/482 ,  H01L29/786

Abstract: A semiconductor device including a biosensor with an on-chip reference electrode embedded within the semiconductor device, and associated manufacturing methods are provided. In some embodiments, a pair of source/drain regions is disposed within a device substrate and separated by a channel region. An isolation layer is disposed over the device substrate. A sensing well is disposed from an upper surface of the isolation layer overlying the channel region. A bio-sensing film is disposed along the upper surface of the isolation layer and extended along sidewall and lower surfaces of the sensing well. A reference electrode is disposed vertically between the bio-sensing film and the isolation layer.

公开(公告)号：US20250159969A1

公开(公告)日：2025-05-15

申请号：US19019957

申请日：2025-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H10D84/03 ,  H10D1/47 ,  H10D30/62 ,  H10D84/01 ,  H10D84/80

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

公开(公告)号：US20230420452A1

公开(公告)日：2023-12-28

申请号：US17848605

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan ,  Wan-Lin Tsai ,  Chung-Liang Cheng

IPC: H01L27/06 ,  H01L29/8605 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/8605 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66166

Abstract: Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

公开(公告)号：US20230381815A1

公开(公告)日：2023-11-30

申请号：US17752558

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yuan Shih ,  Shih-Fen Huang ,  Yan-Jie Liao ,  Wen-Chuan Tai

IPC: B06B1/02

CPC classification number: B06B1/0292

Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form first protrusions and second protrusions, where a first diameter of each of the first protrusions is larger than a second diameter of each of the second protrusions; and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the first protrusions are disposed in the cavity.

公开(公告)号：US20230372970A1

公开(公告)日：2023-11-23

申请号：US17747759

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Jie Liao ,  Shih-Fen Huang ,  Chi-Yuan Shih

IPC: B06B1/02

CPC classification number: B06B1/0292

Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form a plurality of first protrusions in a first region and a plurality of second protrusions in a second region, where a density of the plurality of first protrusions in the first region is different from a density of the plurality of second protrusions in the second region, and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the plurality of first protrusions and the plurality of second protrusions are disposed in the cavity.

公开(公告)号：US11808731B2

公开(公告)日：2023-11-07

申请号：US17135498

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Cheng Huang ,  Yi-Hsien Chang ,  Chin-Hua Wen ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Tung-Tsun Chen ,  Yu-Jie Huang ,  Ching-Hui Lin ,  Sean Cheng ,  Hector Chang

IPC: G01N27/414 ,  B01L3/00 ,  B01F31/85 ,  B01F33/30 ,  H10N30/00 ,  H10N30/20 ,  G01N33/543 ,  C12Q1/6825

CPC classification number: G01N27/4145 ,  B01F31/85 ,  B01F33/30 ,  B01F33/3045 ,  B01L3/502707 ,  B01L3/502715 ,  B01L3/502761 ,  B01L3/502792 ,  G01N33/5438 ,  H10N30/1051 ,  H10N30/2042 ,  H10N30/2047 ,  B01L2200/12 ,  B01L2300/06 ,  B01L2300/0645 ,  B01L2300/0663 ,  B01L2300/0819 ,  B01L2300/0887 ,  B01L2300/1827 ,  C12Q1/6825

Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.

公开(公告)号：US11456330B2

公开(公告)日：2022-09-27

申请号：US16534330

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yuan Shih ,  Shih-Fen Huang ,  You-Ru Lin ,  Yan-Jie Liao

IPC: H01L41/31 ,  H01L27/20 ,  H01L41/314 ,  H01L41/09

Abstract: In some embodiments, the present disclosure relates to a method for recovering degraded device performance of a piezoelectric device. The method includes operating the piezoelectric device in a performance mode by applying one or more voltage pulses to the piezoelectric device, and determining that a performance parameter of the piezoelectric device has a first value that has deviated from a reference value by more than a predetermined threshold value during a first time period. During a second time period, the method further includes applying a bipolar loop to the piezoelectric device, comprising positive and negative voltage biases. During a third time period, the method further includes operating the piezoelectric device in the performance mode, wherein the performance parameter has a second value. An absolute difference between the second value and the reference value is less than an absolute difference between the first value and the reference value.

公开(公告)号：US11063157B1

公开(公告)日：2021-07-13

申请号：US16728452

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L29/94 ,  H01L49/02 ,  H01L23/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/764

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

公开(公告)号：US10955379B2

公开(公告)日：2021-03-23

申请号：US16400500

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Fu-Chun Huang

IPC: G01N27/414 ,  G01N27/30 ,  B01L3/00

Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.